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91. 发明授权

US07468901B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07468901B2
公开(公告)日：2008-12-23
申请号：US11399397
申请日：2006-04-07
申请人： Norifumi Kameshiro , Riichiro Takemura , Tomoyuki Ishii
发明人： Norifumi Kameshiro , Riichiro Takemura , Tomoyuki Ishii
IPC分类号： G11C7/00
CPC分类号： G11C11/405 , G11C7/18 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108
摘要： In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.
摘要翻译：在双晶体管增益单元结构中，提供了能够稳定读取而没有故障并且具有小面积存储单元的半导体存储器件。在具有写晶体管和读晶体管的双晶体管增益单元存储器中，分别提供写字线，读字线，写位线和读位线，并且独立地设置要施加的电压。此外，存储单元连接到与相邻存储单元相同的读字线和写位线。

92. 发明申请

US20080013366A1 DEVICE AND METHOD HAVING A MEMORY ARRAY STORING EACH BIT IN MULTIPLE MEMORY CELLS 失效
标题翻译：具有在多个存储器单元中存储每个位的存储器阵列的设备和方法
公开(公告)号：US20080013366A1
公开(公告)日：2008-01-17
申请号：US11777749
申请日：2007-07-13
申请人： Michael Shore
发明人： Michael Shore
IPC分类号： G11C11/24
CPC分类号： G11C8/12 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/403 , G11C11/4082 , G11C11/4085 , G11C11/4087 , G11C29/74 , G11C29/781 , G11C29/783 , G11C29/80 , G11C29/88 , G11C2211/4013
摘要： A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells.
摘要翻译：提供了一种存储器阵列，其具有为每个行地址访问的至少两个存储器单元，以保持足够的电荷以正确地存储“1”和“0”位。对于这样的存储器阵列，阵列中的偶数行解码器和奇数行解码器被永久地启用，使得阵列接收的每个行地址使得偶数行解码器激励至少一个偶数字线，并且奇数行解码器激励至少一个奇数字线。结果，对于每个行地址访问至少两个存储单元，使得每个“1”或“0”位作为电荷存储在至少两个存储单元中。

93. 发明申请

US20070139995A1 Semiconductor memory device 审中-公开
公开(公告)号：US20070139995A1
公开(公告)日：2007-06-21
申请号：US11705420
申请日：2007-02-13
申请人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
IPC分类号： G11C5/06 , G11C8/00 , G11C11/24
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C11/4074 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10882
摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.

94. 发明授权

US07212450B2 FeRAM having differential data 失效
标题翻译： FeRAM具有差分数据
公开(公告)号：US07212450B2
公开(公告)日：2007-05-01
申请号：US10879138
申请日：2004-06-30
申请人： Jae Hyoung Lim , Dong Yun Jeong , Hee Bok Kang
发明人： Jae Hyoung Lim , Dong Yun Jeong , Hee Bok Kang
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/06 , G11C11/22 , G11C2211/4013
摘要： Disclosed is a non-volatile ferroelectric memory device having differential data, the device including: a plurality of cell array block groups having a hierarchy bit line structure and storing differential data; a common data bus being shared by a plurality of the cell array block groups, and transferring sensing voltages induced by the differential data; a column selection control unit selectively applying to the common data bus the induced sensing voltages of two main bit lines of the cell array block group according to the differential data; and a sense amp unit receiving the sensing voltages through the common data bus, comparing two sensing voltages induced by the differential data, and sensing the cell data. Therefore, the non-volatile ferroelectric memory device of the invention is capable of sensing a cell data more stably, independent of external factors and the state of a cell, by simultaneously sensing the stored data (differential data) in two unit cells and detecting the cell data.
摘要翻译：公开了一种具有差分数据的非挥发性铁电存储器件，该器件包括：具有层级位线结构并存储差分数据的多个单元阵列块组; 公共数据总线由多个单元阵列块组共享，并传送由差分数据引起的感测电压; 列选择控制单元根据差分数据选择性地向公共数据总线施加单元阵列块组的两个主位线的感应感测电压; 以及感测放大器单元，其通过公共数据总线接收感测电压，比较由差分数据感应的两个感测电压，并感测单元数据。因此，本发明的非挥发性铁电存储器件能够通过同时检测两个单元电池中存储的数据（差分数据）并且检测单元电池的数据，从而能够更独立于外部因素和单元的状态来感测电池数据细胞数据。

95. 发明授权

US07203123B2 Integrated DRAM memory device 有权
标题翻译：集成DRAM存储器件
公开(公告)号：US07203123B2
公开(公告)日：2007-04-10
申请号：US11006865
申请日：2004-12-08
申请人： Peter Pöchmüller
发明人： Peter Pöchmüller
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G06F12/06 , G11C7/08 , G11C7/18 , G11C11/4091 , G11C2207/065 , G11C2211/4013
摘要： An integrated memory device including a number of memory blocks including memory cells wherein the memory cells are arranged in a matrix of wordlines and bitlines, wherein the number of memory blocks including a first set of memory blocks the memory cells thereof having a first random access time and a second set of memory blocks the memory cells thereof having a second random access time, wherein the second random access time is smaller that the first random access time.
摘要翻译：一种包括多个存储块的集成存储器件，包括存储器单元，其中存储器单元被布置在字线和位线的矩阵中，其中包括第一组存储器的存储器块的数量将其存储单元具有第一随机存取时间以及第二组存储器，其存储单元具有第二随机存取时间，其中所述第二随机存取时间小于所述第一随机存取时间。

96. 发明申请

US20060197115A1 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US20060197115A1
公开(公告)日：2006-09-07
申请号：US10551702
申请日：2003-04-03
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： H01L29/768
CPC分类号： G11C13/0004 , G11C5/02 , G11C7/18 , G11C13/0007 , G11C2211/4013 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A phase change memory device has a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of the memory cells, bit lines each commonly connecting one ends of plural memory cells arranged along a first direction of the matrix and word lines each commonly connecting the other ends of plural memory cells arranged along a second direction of the matrix; a read/write circuit formed on the semiconductor substrate as underlying the cell arrays for reading and writing data of the cell arrays; first and second vertical wirings disposed outside of first and second boundaries that define a cell layout region of the cell arrays in the first direction to connect the bit lines of the respective cell arrays to the read/write circuit; and third vertical wirings disposed outside of one of third and fourth boundaries that define the cell layout region in the second direction to connect the word lines of the respective cell arrays to the read/write circuit.
摘要翻译：相变存储器件具有半导体衬底; 多个单元阵列，堆叠在半导体衬底之上，每个单元阵列具有以矩阵方式布置的存储单元，用于存储电阻值，作为通过存储单元的相变确定的数据，各通常连接多个存储单元的一端的位线沿着矩阵的第一方向布置，每个字线通常连接沿矩阵的第二方向布置的多个存储单元的另一端; 在半导体衬底上形成的用于读取和写入单元阵列数据的单元阵列的读/写电路; 布置在第一和第二边界之外的第一和第二垂直布线，其限定第一方向上的单元阵列的单元布局区域，以将各单元阵列的位线连接到读/写电路; 以及第三垂直布线，其布置在第三和第四边界之一之外，其限定第二方向上的单元布局区域，以将各单元阵列的字线连接到读/写电路。

97. 发明申请

US20060109731A1 Twin-cell bit line sensing configuration 失效
标题翻译：双电池位线检测配置
公开(公告)号：US20060109731A1
公开(公告)日：2006-05-25
申请号：US10992826
申请日：2004-11-19
申请人： Jungwon Suh , Jong-Hoon Oh
发明人： Jungwon Suh , Jong-Hoon Oh
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C7/18 , G11C2211/4013
摘要： Twin-cell bit line sensing structures and techniques are provided. Utilizing a folded bit line like structure, with bit line and complementary bit lines located together, sense amplifiers can be between cell arrays. Bit line switches, responsive to activated word lines in an array, may be used to selectively couple bit line pairs of the shared arrays with the sense amplifiers with a single word line activation.
摘要翻译：提供双电池位线感测结构和技术。利用折叠的位线结构，位线和互补位线位于一起，感测放大器可以在单元阵列之间。响应于阵列中激活的字线的位线开关可用于通过单个字线激活来选择性地将共享阵列的位线对与读出放大器耦合。

98. 发明授权

US06992343B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06992343B2
公开(公告)日：2006-01-31
申请号：US10975494
申请日：2004-10-29
申请人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
发明人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108 , G11C7/18 , G11C11/403 , G11C11/406 , G11C11/40615 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814 , H01L27/10885 , H01L27/10897 , Y10S257/905 , Y10S257/906
摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.
摘要翻译：提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期来实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低，高速读出时间，确保自刷新时间长的刷新周期。采用单交点单元两个单元/比特方法的DRAM具有采用单交叉6F 单元的双单元结构，其结构是：将存储单元布置在与位线对和字线之间的交点; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。此外，在硅衬底中形成每个存储单元的晶体管的源极，沟道和漏极的有源区相对于位线对的方向倾斜地形成。

99. 发明申请

US20050219893A1 Semiconductor memory device having dummy word line 失效
标题翻译：具有虚拟字线的半导体存储器件
公开(公告)号：US20050219893A1
公开(公告)日：2005-10-06
申请号：US11131384
申请日：2005-05-18
申请人： Yasuhiko Tsukikawa , Takashi Ito
发明人： Yasuhiko Tsukikawa , Takashi Ito
IPC分类号： H01L27/108 , G11C7/18 , G11C11/401 , G11C11/404 , G11C11/405 , G11C11/4097 , H01L21/8242 , H01L27/02 , G11C11/24
CPC分类号： H01L27/10882 , G11C7/18 , G11C11/405 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814
摘要： Each cell unit has a cell plate electrically isolated from the cell plates in the other cell units.
摘要翻译：每个电池单元具有与其它电池单元中的电池板电隔离的电池板。

100. 发明授权

US06909644B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06909644B2
公开(公告)日：2005-06-21
申请号：US09791815
申请日：2001-02-26
申请人： Shinya Fujioka , Hitoshi Ikeda , Masato Matsumiya
发明人： Shinya Fujioka , Hitoshi Ikeda , Masato Matsumiya
IPC分类号： G11C11/409 , G11C11/00 , G11C11/401 , G11C11/405 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/00
CPC分类号： G11C7/065 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/002 , G11C2207/005 , G11C2211/4013
摘要： The present invention provides a semiconductor memory device of a twin-storage type having an operation control method and a circuit structure that achieve a higher process rate, a less power consumption, and a smaller chip area. This semiconductor memory device includes bit lines in pairs, a sense amplifier connected to each pair of the bit lines, a first memory cell connected to one bit line of each pair of the bit lines, a second memory cell that is connected to the other bit line of each pair of the bit lines and stores the inverted data of the data stored in the first memory cell. This semiconductor memory device is characterized by not having means to pre-charge the bit lines to a predetermined potential. The semiconductor memory device of the present invention is also characterized by including a control circuit that controls the sense amplifier to start a pull-down operation after starting a pull-up operation.
摘要翻译：本发明提供一种双存储型半导体存储器件，其具有实现更高处理速率，更少功耗和更小芯片面积的操作控制方法和电路结构。该半导体存储器件包括成对的位线，连接到每对位线的读出放大器，连接到每对位线的一个位线的第一存储器单元，连接到另一个位的第二存储器单元并且存储存储在第一存储单元中的数据的反相数据。该半导体存储器件的特征在于没有将位线预充电到预定电位的装置。本发明的半导体存储器件的特征还在于包括控制电路，其控制读出放大器在开始上拉操作之后开始下拉操作。

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