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91. 发明申请

WO2004029971A3 HYBRID FUSES FOR REDUNDANCY 审中-公开
标题翻译：用于冗余的混合熔断器
公开(公告)号：WO2004029971A3
公开(公告)日：2004-06-03
申请号：PCT/EP0310468
申请日：2003-09-19
申请人： INFINEON TECHNOLOGIES AG , TOSHIBA KK
发明人： JOACHIM HANS-OLIVER , MIYAKAWA TADASHI , REHM NORBERT , ROEHR THOMAS
IPC分类号： G11C29/00
CPC分类号： G11C29/785 , G11C17/14
摘要： A redundancy unit (204) comprising first (260) and second (270) fuse blocks for programming the redundancy element (220) is disclosed. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before and after packaging.
摘要翻译：公开了一种包括用于对冗余元件（220）进行编程的第一（260）和第二（270））熔丝块的冗余单元（204）。一个保险丝盒有激光熔断保险丝和其他电气保险丝。冗余单元可以通过任一个保险丝块进行编程，使得冗余单元能够用于包装之前和之后识别的缺陷。

92. 发明申请

WO2004015778A1 NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：WO2004015778A1
公开(公告)日：2004-02-19
申请号：PCT/JP2003/010017
申请日：2003-08-06
申请人： CANON KABUSHIKI KAISHA , HIRAI, Tadahiko , SATO, Naotake
发明人： HIRAI, Tadahiko , SATO, Naotake
IPC分类号： H01L27/10
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/34 , G11C17/14 , H01L27/101 , H01L27/28
摘要： The invention provides a nonvolatile memory device that enables formation of integrated circuits on a substrate such as glass and resin substrates and selection of a desired cell, where the nonvolatile memory device comprises a matrix wiring, a switching element, and a memory element, wherein the memory has a changeable impedance, and both the switching element and the memory element comprises an organic semiconductor or an organic electric conductor or both.
摘要翻译：本发明提供了一种非易失性存储器件，其能够在诸如玻璃和树脂基板的基板上形成集成电路，并且选择期望的单元，其中非易失性存储器件包括矩阵布线，开关元件和存储元件，其中，存储器具有可变阻抗，并且开关元件和存储元件都包括有机半导体或有机电导体或两者。

93. 发明申请

WO03032372A8 A THREE-DIMENSIONAL MEMORY 审中-公开
标题翻译：一个三维的记忆
公开(公告)号：WO03032372A8
公开(公告)日：2003-09-18
申请号：PCT/CN0200703
申请日：2002-09-29
申请人： ZHANG GUOBIAO
发明人： ZHANG GUOBIAO
IPC分类号： G11C7/18 , G11C29/00 , H01L27/06 , H01L21/00
CPC分类号： H01L29/76 , G11C7/18 , G11C17/06 , G11C17/14 , G11C29/822 , G11C29/846 , H01L23/58 , H01L27/0688
摘要： In a three-dimensional integrated memory (3DiM), three-dimensional memories (3D-Ms) are integrated with conventional readable and writeable memories and/or data processors on a single chip. The overall performance of a 3DiM (such as speed, rate of finished products, programmability and data security) is superior to that of standalone 3D-Ms. The invention provides various types of methodsfor improving the capability of integration of said 3D-Ms. In addition, the invention also provides further improvement in the structure, circuit design and the like of 3D-Ms. One important application field of 3D-Ms is the integrated circuit testing : a 3D-M loaded with test data may be integrated with a test circuit, and thereby realize self-testing and high-speed testing on the spot.
摘要翻译：在三维集成存储器（3DiM）中，三维存储器（3D-Ms）与传统的可读和可写存储器和/或数据处理器集成在单个芯片上。 3DiM的整体性能（如速度，成品率，可编程性和数据安全性）优于独立式3D-Ms。本发明提供了各种提高3D-Ms整合能力的方法。另外，本发明还提供了3D-Ms的结构，电路设计等方面的进一步改进。 3D-Ms的一个重要应用领域是集成电路测试：装载有测试数据的3D-M可以与测试电路集成，从而实现现场自检和高速测试。

94. 发明申请

WO03071554A2 FUSE CONCEPT AND METHOD OF OPERATION 审中-公开
标题翻译：保险丝的概念和操作方法
公开(公告)号：WO03071554A2
公开(公告)日：2003-08-28
申请号：PCT/EP0301630
申请日：2003-02-18
申请人： INFINEON TECHNOLOGIES AG
发明人： HOENIGSCHMID HEINZ , VIEHMANN HEINRICH
IPC分类号： G11C29/04 , G11C17/14 , G11C29/00 , G11C29/44
CPC分类号： G11C11/16 , G11C17/14 , G11C29/72 , G11C29/789
摘要： It is difficult to fabricate a semiconductor memory device without any faulty memory storage cells. One solution is to produce more storage cells than needed on a device and faulty storage cells are replaced by the redundant storage cells. This solution requires that the addresses of the faulty storage cells, along with the replacement storage cells, be saved in a memory. The present invention teaches the use of non-volatile memory cells, particularly magnetoresistive random access memory (MRAM) cells, to store the addresses. Non-volatile memory cells can effectively replace the laser fuses currently used and also provides an advantage in the elimination of the laser fuse-burning step during the fabrication of the device.
摘要翻译：难以制造半导体存储器件而没有任何错误的存储器存储单元。一个解决方案是生产比设备上所需的更多的存储单元，并且冗余存储单元被替换为故障存储单元。该解决方案要求将故障存储单元的地址与替换存储单元一起保存在存储器中。本发明教导了使用非易失性存储单元，特别是磁阻随机存取存储器（MRAM）单元来存储地址。非易失性存储单元可以有效地替代当前使用的激光熔丝，并且还在设备制造期间消除激光熔丝烧制步骤的优点。

95. 发明申请

WO2003052890A1 PROCESSING A MEMORY LINK WITH A SET OF AT LEAST TWO LASER PULSES 审中-公开
标题翻译：用一组至少两个激光脉冲处理存储器链接
公开(公告)号：WO2003052890A1
公开(公告)日：2003-06-26
申请号：PCT/US2002/040410
申请日：2002-12-17
申请人： ELECTRO SCIENTIFIC INDUSTRIES, INC. , SUN, Yunlong , SWENSON, Edward, J. , HARRIS, Richard, S.
发明人： SUN, Yunlong , SWENSON, Edward, J. , HARRIS, Richard, S.
IPC分类号： H01S3/10
CPC分类号： H01S3/0057 , B23K26/0604 , B23K26/0613 , B23K26/0622 , B23K26/0624 , B23K26/067 , G11C17/14 , G11C17/143 , H01L23/5258 , H01L2924/0002 , H01S5/4012 , H01L2924/00
摘要： A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 500 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within a range of about 0.1 ps to 30 ns. The set (50) can be treated as a single "pulse" by conventional laser positioning systems (62) to perform on-the-fly link removal without stopping whenever the laser system (60) fires a set (50) of laser pulses (52) at each link (22). Conventional IR wavelengths or their harmonics can be employed.
摘要翻译：激光脉冲（52）的组（50）被用于切断存储器或其他IC芯片中的导电链路（22）。该组（50）的持续时间优选短于500ns; 并且该组（50）内的每个激光脉冲（52）的脉冲宽度优选在约0.1ps至30ns的范围内。该组（50）可以被视为单个“脉冲” 通过传统的激光定位系统（62）在每个激光系统（60）在每个链路（22）处激发一组（50个）激光脉冲（52）时执行即时链路移除而不停止。传统的红外波长或它们的谐波可以被采用。

96. 发明申请

WO9747041A3 PROGRAMMABLE, NON-VOLATILE MEMORY DEVICE, AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：可编程的，非易失性存储器件，以及制造这种器件的方法
公开(公告)号：WO9747041A3
公开(公告)日：1998-01-22
申请号：PCT/IB9700582
申请日：1997-05-22
申请人： PHILIPS ELECTRONICS NV , PHILIPS NORDEN AB
发明人： KRAMER NIELS , NIESTEN MAARTEN JOSEPH HUBERTU , LODDERS WILHELMUS HUBERTUS MAR , OVERSLUIZEN GERRIT
IPC分类号： G11C17/06 , G11C11/36 , G11C16/02 , G11C17/14 , H01L21/3065 , H01L21/822 , H01L27/10 , H01L27/105 , H01L27/115
CPC分类号： G11C16/02 , G11C17/14 , H01L21/822 , H01L27/10
摘要： The invention relates to an erasable non-volatile memory in which a diode is formed at each point of intersection between the x-selection lines (Ki) and y-selection lines (Rj), of which diode the anode and cathode are conductively connected to the x- and y- selection lines. The diodes are formed in hydrogenated amorphous silicon or silicon compounds such as amorphous Si1-xGex. Writing takes place by means of a current pulse through selected diodes. The current in the forward direction becomes much lower, for example a few hundred times lower, than in diodes which are not selected, probably owing to degradation in the semiconductor material. The diodes may be returned to their original state again (i.e. be erased) through heating, for example at a temperature of 200 °C during 100 minutes. Preferably, the diodes are formed by Schottky diodes because the characteristic in the reverse direction does not (substantially) change in this type of diode. The Schottky diodes may be formed in the transitional region between the amorphous intrinsic semiconductor material (6) and the selection lines (Ki).

97. 发明公开

EP3276628A1 ADAPTABLE SENSE CIRCUITRY AND METHOD THEREFOR 审中-公开
标题翻译：适应性感测电路及其方法
公开(公告)号：EP3276628A1
公开(公告)日：2018-01-31
申请号：EP17182842.9
申请日：2017-07-24
申请人： NXP USA, Inc.
发明人： Yang, Jianan
IPC分类号： G11C7/14 , G11C7/12 , G11C17/12 , G11C17/14 , G11C17/18
CPC分类号： G11C7/12 , G11C7/065 , G11C7/067 , G11C7/08 , G11C7/14 , G11C17/12 , G11C17/14 , G11C17/18
摘要： Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM.
摘要翻译：公开了用于操作只读存储器（ROM）的设备和方法。用于操作ROM的方法包括利用耦合到虚拟位线的虚拟感测放大器来感测虚拟位线以产生保持器调整信号。基于保持器调整信号，调整耦合到读出放大器电路的保持器电路的保持器强度。读出放大器电路能够读出存储在ROM中的数据。

98. 发明公开

EP3022738A1 RESISTANCE-BASED MEMORY CELLS WITH MULTIPLE SOURCE LINES 有权
标题翻译： WIDERSTANDSSPEICHERZELLEN MIT MEHREREN QUELLLEITUNGEN
公开(公告)号：EP3022738A1
公开(公告)日：2016-05-25
申请号：EP14776976.4
申请日：2014-09-18
申请人： Qualcomm Incorporated
发明人： DONG, Xiangyu
IPC分类号： G11C11/00 , G11C11/16 , G11C11/56 , G11C13/00 , G11C17/02 , G11C17/14 , G11C7/10 , G11C8/16
CPC分类号： G11C11/1673 , G11C7/1075 , G11C8/16 , G11C11/005 , G11C11/16 , G11C11/1659 , G11C11/56 , G11C11/5671 , G11C13/0002 , G11C17/02 , G11C17/14 , G11C2213/74 , G11C2213/79
摘要： In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value.
摘要翻译：在特定实施例中，器件包括具有多个源极线和多个存取晶体管的基于电阻的存储单元。多路存取晶体管与多条源极线的耦合配置对数据值进行编码。

99. 发明授权

EP1800323B1 LOW VOLTAGE PROGRAMMABLE eFUSE WITH DIFFERENTIAL SENSING SCHEME 有权
标题翻译：可编程低压差分的eFuse读法
公开(公告)号：EP1800323B1
公开(公告)日：2011-11-16
申请号：EP05794850.7
申请日：2005-09-01
申请人： International Business Machines Corporation
发明人： OUELLETTE, Michael, R. , WISSEL, Larry
IPC分类号： H01H37/76 , G11C17/16 , G11C17/18 , G11C29/02 , G11C29/50
CPC分类号： G11C29/027 , G11C17/14 , G11C17/16 , G11C17/18 , G11C29/02 , G11C29/50 , H01L2924/0002 , H01L2924/00
摘要： A low voltage programmable electronic fuse structure incorporating a differential sensing scheme is disclosed for integrated circuits. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse (xF[j]) caused by the sense operation. The magnitude of the current required for sensing is reduced another factor of two because a reference fuse (xF) and the fuse to be programmed (xF[ j]) are coupled in series, whereas during programming only the programmed fuse (xF[j]) limits the programming current. During the sense operation a gating transistor (mNR) emulates the voltage drop across a fuse select transistor (g[j]) for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse are also disclosed.

100. 发明授权

EP1999757B1 VERFAHREN ZUM PROGRAMMIEREN EINER ELEKTRONISCHEN SCHALTUNG SOWIE ELEKTRONISCHE SCHALTUNG 有权
标题翻译：方法编程的电子电路和电子电路
公开(公告)号：EP1999757B1
公开(公告)日：2010-09-08
申请号：EP07723469.8
申请日：2007-03-21
申请人： PolyIC GmbH & Co. KG
发明人： ULLMANN, Andreas , FIX, Walter
IPC分类号： G11C17/00 , G06K19/07
CPC分类号： G11C13/00 , B82Y10/00 , G11C13/0014 , G11C17/00 , G11C17/14 , G11C2213/80
摘要： The invention relates to a method for producing an electronic circuit and to an electronic circuit, which has at least one organic electric functional layer and at least one data storage unit, the latter being configured with two electrically conductive layer contacts. The two electrically conductive layer contacts lie next to one another and are electrically interconnected by an electrically conductive dry substance, such as dried ink, or by an electrically conductive solidified substance.

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