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91. 发明专利

JP3514502B2 Mantissa addition system for the floating point adder 失效
公开(公告)号：JP3514502B2
公开(公告)日：2004-03-31
申请号：JP2604794
申请日：1994-01-28
申请人：モトローラ・インコーポレイテッド
发明人：アリック・エイナブ , イェフダ・ボルパート , ヨラム・ホーレン
IPC分类号： G06F7/00 , G06F7/485 , G06F7/50 , G06F7/507 , G06F7/74 , G06F7/76 , G06F5/01
CPC分类号： G06F7/74 , G06F7/485

92. 发明公开

EP2243074A2 PROCESSOR AND METHOD OF DETERMINING A NORMALIZATION COUNT 审中-公开
标题翻译：处理器和一种用于确定归一化COUNT
公开(公告)号：EP2243074A2
公开(公告)日：2010-10-27
申请号：EP09700938.5
申请日：2009-01-09
申请人： QUALCOMM Incorporated
发明人： KRITHIVASAN, Shankar , PLONDKE, Erich J. , CODRESCU, Lucian , ZENG, Mao
IPC分类号： G06F7/483 , H03K21/00 , H03K23/00
CPC分类号： G06F7/74 , G06F7/49936
摘要： In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.

93. 发明授权

EP0992917B1 Linear vector computation 有权
标题翻译： Linearvektorrechnung
公开(公告)号：EP0992917B1
公开(公告)日：2007-07-04
申请号：EP98402465.3
申请日：1998-10-06
申请人： TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
发明人： Djafarian, Karim , Laurenti, Gilbert , Clave, Gael
IPC分类号： G06F17/16
CPC分类号： G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F7/764 , G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30072 , G06F9/3012 , G06F9/30145 , G06F9/30149 , G06F9/32 , G06F9/321 , G06F9/325 , G06F9/3552 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3867 , G06F9/3879 , G06F9/3885 , G06F9/3891 , G06F17/16
摘要： A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient register 940 for holding a representation of each of N coefficients of a first input vector. A test unit 950 is provided for testing selected parts (e.g. bits) of the coefficient register for respective coefficient representations. An arithmetic unit 970 computes respective coordinates of an output vector by selective addition/subtraction of coordinates of a second input vector dependent on results of the coefficient representation tests. Power consumption can be kept low due to the use of a coefficient test operation in parallel with an ALU operation. Each coordinate of an output vector Y can be computed with a N+1 step algorithm, the computation being done with bit test unit operating in parallel with an ALU according to the following equation: At a step (i + 1)1≤i≤N of the computation, a bit Ci+1 of the CPU register is addressed, this bit is tested in a temporary register and a conditional addition/subtraction of a coordinate of the second input vector Xij is performed.

94. 发明授权

EP1230591B1 DECOMPRESSION BIT PROCESSING WITH A GENERAL PURPOSE ALIGNMENT TOOL 有权
标题翻译：有减压VIEKSEITIGEN对齐工具位处理
公开(公告)号：EP1230591B1
公开(公告)日：2007-01-03
申请号：EP00980554.0
申请日：2000-11-16
申请人： SUN MICROSYSTEMS, INC.
发明人： SUDHARSANAN, Subramania , CHAN, Jeffrey, Meng, Wah , TREMBLAY, Marc
IPC分类号： G06F9/30 , G06F9/315 , G06F7/00
CPC分类号： G06F7/74 , G06F9/30018 , G06F9/30032
摘要： A method and apparatus for performing single-instruction bit field extraction and for counting a number of leading zeros in a sequence of bits on a general purpose processor are provided. The fast bit extraction operations are accomplished by executing a first instruction for extracting an arbitrary number of bits of a sequence of bits stored in two or more source registers of the processor starting at an arbitrary offset and the storing the extracted bits in a destination register. Both the source and the destination registers are specified by the instruction. In addition, a second instruction is provided for counting the number of leading zeros in a sequence of bits stored in two or more source registers of the processor and then storing a binary value representing the number of leading zeros in a destination register. Again the source and the destination registers are specified by the second instruction. Both the first and the second instructions are pipelined to obtain an effective throughput of one instruction every cycle, respectively. As a result, bit extraction operations are performed very efficiently by the processor, thereby reducing the overall processing time required to compress and decompress multimedia data.

95. 发明公开

EP1727150A2 Physical priority encoder 审中-公开
标题翻译： PhysikalischerPrioritätskodierer
公开(公告)号：EP1727150A2
公开(公告)日：2006-11-29
申请号：EP06251760.2
申请日：2006-03-30
申请人： STMicroelectronics, Inc.
发明人： Lysinger, Mark
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G06F7/74 , G11C15/00 , G11C15/04
摘要： A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operatively connected to the array of CAM cells and determines a highest priority matching address for data within the array of CAM cells. The priority encoder includes match lines associated with respective rows and precharged bus lines connected into respective match lines that are discharged whenever there is a match signal such that the highest precharged bus line discharged results in an encoded address.
摘要翻译：优先编码器可以用于通常具有排列成列和行的CAM单元阵列的内容寻址存储器（CAM）设备，每个行具有指示比较数据具有相应行内的匹配数据的匹配信号。优先编码器可操作地连接到CAM单元阵列，并确定CAM单元阵列内的数据的最高优先级匹配地址。优先编码器包括与相应行相关联的匹配线和连接到相应匹配线中的预充电总线，每当匹配信号被放电时，放电的最高预充电总线导致编码地址。

96. 发明授权

EP0853789B1 FLEXIBLE IMPLEMENTATION OF A SYSTEM MANAGEMENT MODE (SMM) IN A PROCESSOR 失效
标题翻译：管理员在处理器灵活的实现
公开(公告)号：EP0853789B1
公开(公告)日：2004-03-03
申请号：EP96935972.8
申请日：1996-10-03
申请人： ADVANCED MICRO DEVICES INC.
发明人： FAVOR, John, G. , WEBER, Frederick, D.
IPC分类号： G06F9/46 , G06F9/445
CPC分类号： G06F7/74 , G06F9/30152 , G06F9/30167 , G06F9/30174 , G06F9/30185 , G06F9/3802 , G06F9/3806 , G06F9/3812 , G06F9/3816 , G06F9/382 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/445 , G06F9/45533 , G06F9/4812
摘要： A system management mode (SMM) (900) of operating a processor (120) includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is 'soft' and freely defined. A system management interrupt (SMI) pin (960) is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode. SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access.

97. 发明授权

EP0853780B1 SUPERSCALAR MICROPROCESSOR WITH RISC86 INSTRUCTION SET 失效
标题翻译： WITH RISC86命令集超标量微处理器
公开(公告)号：EP0853780B1
公开(公告)日：2003-08-06
申请号：EP96933908.4
申请日：1996-10-04
申请人： Advanced Micro Devices, Inc.
发明人： FAVOR, John, G.
IPC分类号： G06F9/30 , G06F9/318 , G06F9/26
CPC分类号： G06F7/74 , G06F9/30152 , G06F9/30167 , G06F9/3017 , G06F9/30174 , G06F9/30185 , G06F9/324 , G06F9/3806 , G06F9/3812 , G06F9/3816 , G06F9/382 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3853 , G06F9/3861 , G06F9/45533 , G06F9/4812

98. 发明授权

EP0853787B1 SCAN CHAIN FOR RAPIDLY IDENTIFYING FIRST OR SECOND OBJECTS OF SELECTED TYPES IN A SEQUENTIAL LIST 失效
标题翻译：扫描快速检测选定类型的在第一和第二对象的顺序列表
公开(公告)号：EP0853787B1
公开(公告)日：2003-07-02
申请号：EP96936103.9
申请日：1996-10-04
申请人： ADVANCED MICRO DEVICES INC.
发明人： FAVOR, John, G. , BEN-MEIR, Amos , TRULL, Jeffrey, E.
IPC分类号： G06F9/38 , G06F7/00
CPC分类号： G06F7/74 , G06F9/30149 , G06F9/30167 , G06F9/30174 , G06F9/3812 , G06F9/382 , G06F9/3822 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3853

99. 发明公开

EP0992882A3 Bit field processor 审中-公开
标题翻译： Bitfeldprozessor
公开(公告)号：EP0992882A3
公开(公告)日：2003-03-05
申请号：EP99400557.7
申请日：1999-03-08
申请人： TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
发明人： Laurenti, Gilbert , Giacalone, Jean-Pierre , Ego, Manuel, Le Mas des Micocouliers A1 , Couvrat, Marc
IPC分类号： G06F7/00 , G06F7/60
CPC分类号： G06F7/764 , G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30014 , G06F9/30018 , G06F9/30149
摘要： The processor can perform bit field expand and bit field extract functions under mask, as shown in figure 10. This functionality is particularly useful for the normalisation of floating-point numbers. The circuitry comprises encoders (1306-1312,1612-1618) and number-of-one-counters (1202-1236,1302) both partitioned in slices of 4 bits, and a two-level selector (1314-1322,1604-1608).

100. 发明公开

EP0992906A3 Software breakpoint in a delay slot 有权
标题翻译：延迟时隙期间软件断点
公开(公告)号：EP0992906A3
公开(公告)日：2003-01-22
申请号：EP99400558.5
申请日：1999-03-08
申请人： TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
发明人： Abiko, Shigeshi , Laurenti, Gilbert , Buser, Mark , Ponsot, Eric
IPC分类号： G06F11/00 , G06F9/30
CPC分类号： G06F7/764 , G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30018 , G06F9/30032 , G06F9/3005 , G06F9/30076 , G06F9/30149 , G06F9/32 , G06F9/321 , G06F9/3552 , G06F9/3812 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3867 , G06F9/3879 , G06F9/3885 , G06F9/3891
摘要： A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Instructions may be executed during delay slots after program branching while an execution pipeline is being restarted. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A software breakpoint instruction is provided for debugging purposes. In order to correctly emulate the operation of the instruction pipeline when a software breakpoint instruction is executed during a delay slot, the width (1110-1115) of the software breakpoint is the same as the replaced instruction. A limited number of breakpoint instruction length formats (1100, 1102) are combined with non-operational instructions (NOP, NOP_16) to form a large number of combination instructions that match any instruction length format.

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