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91. 发明申请

WO2018071121A1 LATENCY AND BANDWIDTH EFFICIENCY IMPROVEMENT FOR READ MODIFY WRITE WHEN A READ OPERATION IS REQUESTED TO A PARTIALLY MODIFIED WRITE ONLY CACHELINE 审中-公开
标题翻译：读取操作请求读取修改写入的部分修改写入唯一的数据库时延迟和带宽效率改进
公开(公告)号：WO2018071121A1
公开(公告)日：2018-04-19
申请号：PCT/US2017/051034
申请日：2017-09-12
申请人： INTEL CORPORATION
发明人： DASGUPTA, Subhajit , APPU, Abhishek , SURTI, Prasoonkumar
IPC分类号： G06F12/0811
CPC分类号： G06T1/60 , G06F12/0804 , G06F12/0811 , G06F12/0893 , G06F12/128 , G06F2212/1024 , G06F2212/455
摘要： Methods and apparatus relating to techniques to improve/optimize latency and bandwidth efficiency for read modify write operations when a read operation is requested to a partially modified write only cacheline are described. In an embodiment, a first cache stores data from one or more cachelines of a second cache in response to a read hit write only operation (e.g., instead of sending the data to main memory). Write accumulate logic merges the stored data with one or more write operations. Other embodiments are also disclosed and claimed.
摘要翻译：描述了当向读取操作被请求到部分修改的只写高速缓存行时，用于改进/优化读取修改写入操作的等待时间和带宽效率的技术的方法和设备。在一个实施例中，响应于读命中只写操作（例如，而不是将数据发送到主存储器），第一高速缓存存储来自第二高速缓存的一个或多个高速缓存行的数据。写入累积逻辑将存储的数据与一个或多个写入操作合并。其他实施例也被公开和要求保护。

92. 发明申请

WO2018004877A1 REDUCING MEMORY ACCESS LATENCIES DURING RAY TRAVERSAL 审中-公开
标题翻译：减少射线穿透过程中的存储器访问延迟
公开(公告)号：WO2018004877A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/033968
申请日：2017-05-23
申请人： INTEL IP CORPORATION
发明人： WALD, Ingo , BENTHIN, Carsten , WOOP, Sven
IPC分类号： G06F9/30 , G06T1/20 , G06T15/06
CPC分类号： G06T1/60 , G06F12/0207 , G06F12/0811 , G06F12/0862 , G06F2212/1024 , G06F2212/454 , G06F2212/455 , G06F2212/602 , G06F2212/62 , G06T1/20 , G06T15/005 , G06T15/06 , G06T17/005 , G06T2210/12
摘要： While prefetching data for a second fiber, a hierarchical data structure is traversed using a first fiber after deferring traversal for the second fiber. Then context is switched to the second fiber, and the hierarchical data structure is traversed using second fiber while prefetching data for another fiber.
摘要翻译：在预取第二光纤的数据时，在推迟第二光纤的遍历之后，使用第一光纤遍历分层数据结构。然后将上下文切换到第二根光纤，并使用第二根光纤穿过分层数据结构，同时为另一根光纤预取数据。

93. 发明申请

WO2014067440A1 SYSTEMS AND METHODS FOR DYNAMIC DATA STORAGE 审中-公开
标题翻译：动态数据存储的系统和方法
公开(公告)号：WO2014067440A1
公开(公告)日：2014-05-08
申请号：PCT/CN2013/086103
申请日：2013-10-29
申请人： TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
发明人： JIN, Jiesheng
IPC分类号： G06F9/45
CPC分类号： G06F12/126 , G06F2212/455
摘要： A data caching method is performed to receive an instruction to operate based on a specific data set; determine whether the specific data set is cached in its memory; when the specific data set is not cached in the memory, determine a plurality of attributes for a plurality of data sets currently stored in the memory, determine whether these attributes satisfy data caching criteria for storing the specific data set, and furthermore, when the data caching criteria are not satisfied, select at least one of the plurality of data sets according to a data replacement rule, delete at least a portion of the selected data set from the memory, and download the specific data set from a remote source; operate the specific data set according to the user instruction; and store at least a portion of the specific data set in the memory.
摘要翻译：执行数据缓存方法以接收基于特定数据集进行操作的指令; 确定特定数据集是否缓存在其内存中; 当特定数据集不被缓存在存储器中时，确定当前存储在存储器中的多个数据集的多个属性，确定这些属性是否满足用于存储特定数据集的数据缓存标准，此外，当数据缓存标准不满足，根据数据替换规则选择多个数据组中的至少一个，从存储器中删除所选数据集的至少一部分，并从远程源下载特定数据集; 根据用户指令操作具体数据集; 并将特定数据集的至少一部分存储在存储器中。

94. 发明申请

WO2014047050A1 FAST, DYNAMIC CACHE PACKING 审中-公开
标题翻译：快速，动态缓存包装
公开(公告)号：WO2014047050A1
公开(公告)日：2014-03-27
申请号：PCT/US2013/060126
申请日：2013-09-17
申请人： GOOGLE INC.
发明人： HASSE, Chet , LEVIEN, Raphael, Linus , GUY, Romain
IPC分类号： G06F12/04 , G06T1/60
CPC分类号： G06F12/0873 , G06F12/023 , G06F12/04 , G06F2212/455 , G06T1/60 , G09G5/393
摘要： A method for storing information may include determining whether a received data object fits inside a particular one of a plurality of free blocks in a memory bitmap. Each of the plurality of free blocks may include a column of the memory bitmap with a top margin, a bottom margin, and a predetermined width. If the received data object fits, the received data object may be stored in the particular one of the plurality of free blocks, starting at the top margin of the particular one of the plurality of free blocks. The particular one of the plurality of data blocks may be resized by moving the top margin to start below the stored received data object. The determining may include, for each of the plurality of free blocks, a height of the received data object may be compared with a height of each of the free data blocks.
摘要翻译：用于存储信息的方法可以包括确定接收的数据对象是否适合存储器位图中的多个空闲块中的特定一个。多个空闲块中的每一个可以包括具有顶边距，底边距和预定宽度的存储位图的列。如果接收的数据对象适合，则从多个空闲块的特定一个的顶部边缘开始，接收的数据对象可以存储在多个空闲块中的特定的一个中。多个数据块中的特定一个可以通过移动顶部余量来重新调整大小，从而开始于存储的接收数据对象之下。对于多个空闲块中的每一个，确定可以包括将接收到的数据对象的高度与每个空闲数据块的高度进行比较。

95. 发明申请

WO0215011A3 CACHE SYSTEM AND METHOD FOR GENERATING UNCACHED OBJECTS FROM CACHED AND STORED OBJECT COMPONENTS 审中-公开
标题翻译：用于从缓存和存储的对象组件生成未处理对象的高速缓存系统和方法
公开(公告)号：WO0215011A3
公开(公告)日：2002-09-26
申请号：PCT/US0141608
申请日：2001-08-08
申请人： AWARE INC
发明人： GUT RON ABRAHAM , TZANNES ALEXIS PAUL , REITER EDMUND CAMPION
IPC分类号： G06F12/00 , G06F13/00 , G06F17/30 , G11C5/00 , G06F12/08
CPC分类号： G06T1/60 , G06F12/0802 , G06F12/0875 , G06F17/30067 , G06F2212/455
摘要： Methods and apparatus for constructing objects within a cache system thereby allowing the cache system to respond to requested objects that are not initially available within the cache system. One embodiment of the invention caches image files, where the images are divided into components and stored in a format that allows identification and access to the components. The cache system determines that an object, such as an image file, is missing from the cache memory, locates sufficient components from the cache memory and/or external storage, and constructs the object from the located components.
摘要翻译：用于在高速缓存系统内构造对象的方法和设备，从而允许高速缓存系统响应高速缓存系统内最初不可用的请求对象。本发明的一个实施例缓存图像文件，其中图像被分成组件并以允许识别和访问组件的格式存储。高速缓存系统确定从高速缓存存储器中缺少诸如图像文件之类的对象，从高速缓存存储器和/或外部存储器中找到足够的组件，并从所定位的组件构建该对象。

96. 发明申请

WO02015011A2 CACHE SYSTEM AND METHOD FOR GENERATING UNCACHED OBJECTS FROM CACHED AND STORED OBJECT COMPONENTS 审中-公开
标题翻译：用于从缓存和存储的对象组件生成不需要的对象的缓存系统和方法
公开(公告)号：WO02015011A2
公开(公告)日：2002-02-21
申请号：PCT/US2001/041608
申请日：2001-08-08
IPC分类号： G06F12/00 , G06F13/00 , G06F17/30 , G11C5/00
CPC分类号： G06T1/60 , G06F12/0802 , G06F12/0875 , G06F17/30067 , G06F2212/455
摘要： Methods and apparatus for constructing objects within a cache system thereby allowing the cache system to respond to requested objects that are not initially available within the cache system. One embodiment of the invention caches image files, where the images are divided into components and stored in a format that allows identification and access to the components. The cache system determines that an object, such as an image file, is missing from the cache memory, locates sufficient components from the cache memory and/or external storage, and constructs the object from the located components.
摘要翻译：用于在高速缓存系统内构建对象的方法和装置，从而允许高速缓存系统对缓存系统中最初不可用的请求对象做出响应。本发明的一个实施例缓存图像文件，其中图像被分成组件并以允许识别和访问组件的格式存储。高速缓存系统确定高速缓冲存储器中缺少诸如图像文件的对象，从高速缓冲存储器和/或外部存储器中找到足够的组件，并从所定位的组件构建对象。

97. 发明申请

WO2017112182A1 APPARATUS AND METHOD FOR ACCELERATING GRAPH ANALYTICS 审中-公开
标题翻译：用于加速图解分析的装置和方法
公开(公告)号：WO2017112182A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/062784
申请日：2016-11-18
申请人： INTEL CORPORATION
发明人： ANDERSON, Michael , LI, Sheng , PARK, Jong Soo , PATWARY, Md Mostofa Ali , SATISH, Nadathur Rajagopalan , SMELYANSKIY, Mikhail , SUNDARAM, Narayanan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30192 , G06F9/3802 , G06F12/0811 , G06F12/084 , G06F2212/455
摘要： An apparatus and method are described for accelerating graph analytics. For example, one embodiment of a processor comprises: an instruction fetch unit to fetch program code including set intersection and set union operations; a graph accelerator unit (GAU) to execute at least a first portion of the program code related to the set intersection and set union operations and generate results; and an execution unit to execute at least a second portion of the program code using the results provided from the GAU.
摘要翻译：描述了用于加速图分析的装置和方法。例如，处理器的一个实施例包括：指令获取单元，用于获取包括集合交集和设置联合操作的程序代码; 图形加速器单元（GAU），用于执行与所述集合交集有关的程序代码的至少第一部分并设置联合操作并生成结果; 以及执行单元，用于使用从GAU提供的结果来执行程序代码的至少第二部分。

98. 发明申请

WO2016185272A1 SYSTEMS AND METHODS FOR ADDRESSING A CACHE WITH SPLIT-INDEXES 审中-公开
标题翻译：用于解析具有分割索引的高速缓存的系统和方法
公开(公告)号：WO2016185272A1
公开(公告)日：2016-11-24
申请号：PCT/IB2016/000709
申请日：2016-05-11
申请人： LINEAR ALGEBRA TECHNOLOGIES LIMITED
发明人： RICHMOND, Richard
IPC分类号： G06F12/0842 , G06F12/0804 , G06F12/0875 , G06F12/0884 , G06F12/0895
CPC分类号： G06F12/0884 , G06F12/0804 , G06F12/0811 , G06F12/0842 , G06F12/0875 , G06F12/0895 , G06F2212/283 , G06F2212/455
摘要： Cache memory mapping techniques are presented. A cache may contain an index configuration register. The register may configure the locations of an upper index portion and a lower index portion of a memory address. The portions may be combined to create a combined index. The configurable split-index addressing structure may be used, among other applications, to reduce the rate of cache conflicts occurring between multiple processors decoding the video frame in parallel.
摘要翻译：介绍缓存内存映射技术。缓存可以包含索引配置寄存器。寄存器可以配置存储器地址的上索引部分和下索引部分的位置。这些部分可以组合以产生组合索引。除了其他应用之外，可以使用可配置的分拆索引寻址结构来降低在并行解码视频帧的多个处理器之间发生的高速缓存冲突的速率。

99. 发明申请

WO2016175814A1 MAPPING APERTURES OF DIFFERENT SIZES 审中-公开
标题翻译：不同尺寸的贴图
公开(公告)号：WO2016175814A1
公开(公告)日：2016-11-03
申请号：PCT/US2015/028418
申请日：2015-04-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： LILLIBRIDGE, Mark David , FARABOSCHI, Paolo
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F12/1036 , G06F12/023 , G06F12/0292 , G06F12/0804 , G06F2212/1012 , G06F2212/1016 , G06F2212/1041 , G06F2212/302 , G06F2212/455 , G06F2212/657
摘要： Apertures of a first size in a first physical address space of at least one processor are mapped to respective blocks of the first size in a second address space of a storage medium. Apertures of a second size in the first physical address space are mapped to respective blocks of the second size in the second address space, the second size being different from the first size.
摘要翻译：至少一个处理器的第一物理地址空间中的第一大小的孔径被映射到存储介质的第二地址空间中的第一大小的相应块。第二物理地址空间中的第二大小的孔径被映射到第二地址空间中的第二大小的相应块，第二大小与第一大小不同。

100. 发明申请

WO2016118504A1 MEMORY DESCRIPTOR LIST CACHING AND PIPELINE PROCESSING 审中-公开
标题翻译：内存描述符列表缓存和管道处理
公开(公告)号：WO2016118504A1
公开(公告)日：2016-07-28
申请号：PCT/US2016/013909
申请日：2016-01-19
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： WILSON, Mei L. , KRISHNAN, Jitesh , KARIVARADASWAMY, Sathyanarayanan
IPC分类号： G06F13/28 , G06F12/00 , G06F9/00
CPC分类号： G06F13/28 , G06F2212/306 , G06F2212/455 , G06F2212/464
摘要： A method is configured to increase efficiency of buffer usage within a pipeline of a computing device. The method includes creation of a buffer (120) in memory (110) of the computing device and caching of a memory descriptor list (208) by the computing device that describes the buffer in a buffer information cache (122) and has associated therewith a handle (210) that acts as a lookup to the memory descriptor list. The method also includes passing the handle through the pipeline (216) of the computing device for processing of data within the buffer by one or more stages (218,220) of the pipeline such that access to the data is obtained by the one or more stages by using the handle as the lookup as part of a call to obtain the memory descriptor list for the buffer from the buffer information cache.
摘要翻译：一种方法被配置为增加计算设备的流水线内的缓冲器使用的效率。该方法包括在计算设备的存储器（110）中创建缓冲器（120），并且由缓冲器信息高速缓存（122）中描述缓冲器的计算设备对存储器描述符列表（208）进行高速缓存，并且与其相关联 handle（210），用作查询内存描述符列表。该方法还包括将句柄通过计算设备的流水线（216），以便通过流水线的一个或多个阶段（218,220）处理缓冲器内的数据，使得通过一个或多个阶段获得对数据的访问使用句柄作为查询作为调用的一部分，从缓冲区信息缓存获取缓冲区的内存描述符列表。

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