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91. 发明申请

WO2016175814A1 MAPPING APERTURES OF DIFFERENT SIZES 审中-公开
标题翻译：不同尺寸的贴图
公开(公告)号：WO2016175814A1
公开(公告)日：2016-11-03
申请号：PCT/US2015/028418
申请日：2015-04-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： LILLIBRIDGE, Mark David , FARABOSCHI, Paolo
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F12/1036 , G06F12/023 , G06F12/0292 , G06F12/0804 , G06F2212/1012 , G06F2212/1016 , G06F2212/1041 , G06F2212/302 , G06F2212/455 , G06F2212/657
摘要： Apertures of a first size in a first physical address space of at least one processor are mapped to respective blocks of the first size in a second address space of a storage medium. Apertures of a second size in the first physical address space are mapped to respective blocks of the second size in the second address space, the second size being different from the first size.
摘要翻译：至少一个处理器的第一物理地址空间中的第一大小的孔径被映射到存储介质的第二地址空间中的第一大小的相应块。第二物理地址空间中的第二大小的孔径被映射到第二地址空间中的第二大小的相应块，第二大小与第一大小不同。

92. 发明申请

WO2016118504A1 MEMORY DESCRIPTOR LIST CACHING AND PIPELINE PROCESSING 审中-公开
标题翻译：内存描述符列表缓存和管道处理
公开(公告)号：WO2016118504A1
公开(公告)日：2016-07-28
申请号：PCT/US2016/013909
申请日：2016-01-19
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： WILSON, Mei L. , KRISHNAN, Jitesh , KARIVARADASWAMY, Sathyanarayanan
IPC分类号： G06F13/28 , G06F12/00 , G06F9/00
CPC分类号： G06F13/28 , G06F2212/306 , G06F2212/455 , G06F2212/464
摘要： A method is configured to increase efficiency of buffer usage within a pipeline of a computing device. The method includes creation of a buffer (120) in memory (110) of the computing device and caching of a memory descriptor list (208) by the computing device that describes the buffer in a buffer information cache (122) and has associated therewith a handle (210) that acts as a lookup to the memory descriptor list. The method also includes passing the handle through the pipeline (216) of the computing device for processing of data within the buffer by one or more stages (218,220) of the pipeline such that access to the data is obtained by the one or more stages by using the handle as the lookup as part of a call to obtain the memory descriptor list for the buffer from the buffer information cache.
摘要翻译：一种方法被配置为增加计算设备的流水线内的缓冲器使用的效率。该方法包括在计算设备的存储器（110）中创建缓冲器（120），并且由缓冲器信息高速缓存（122）中描述缓冲器的计算设备对存储器描述符列表（208）进行高速缓存，并且与其相关联 handle（210），用作查询内存描述符列表。该方法还包括将句柄通过计算设备的流水线（216），以便通过流水线的一个或多个阶段（218,220）处理缓冲器内的数据，使得通过一个或多个阶段获得对数据的访问使用句柄作为查询作为调用的一部分，从缓冲区信息缓存获取缓冲区的内存描述符列表。

93. 发明申请

WO2016017003A1 コントローラ、および、ホームシステム审中-公开
标题翻译：控制器和家庭系统
公开(公告)号：WO2016017003A1
公开(公告)日：2016-02-04
申请号：PCT/JP2014/070225
申请日：2014-07-31
申请人：三菱電機株式会社
发明人：峯澤　聡司 , 丸山　一郎
IPC分类号： G06F13/00
CPC分类号： G05B19/0426 , G05B2219/25022 , G05B2219/2642 , G06F3/0484 , G06F12/0875 , G06F2212/455 , H04L12/2803
摘要：　各家電機器およびサーバ装置には、各家電機器を管理するための管理画面を構成する各要素データがそれぞれ記憶されている。画面定義データ記憶部(13)は、管理画面の構成内容を定義するデータであり、取得すべき各要素データについてそれぞれ規定された更新仕様を含んだ画面定義データを記憶する。キャッシュデータ記憶部(14)は、各家電機器およびサーバ装置から以前に取得した各要素データを記憶する。画面生成部(151)は、画面定義データに含まれる各更新仕様に基づいて、対応する各要素データを、キャッシュデータ記憶部(14)、または、各家電機器およびサーバ装置からそれぞれ取得して、管理画面を生成する。コントローラ(10)は、生成した管理画面を端末装置に送信して表示させる。
摘要翻译：根据本发明，构成用于管理家用电器的管理屏幕的元件数据被存储在家用电器和服务器装置中。屏幕定义数据存储单元（13）存储定义构成管理屏幕的内容的屏幕定义数据，并且包括为要获取的元素数据规定的更新规范。高速缓存数据存储单元（14）存储先前从家用电器和服务器装置获取的元数据。屏幕生成单元（151）基于屏幕定义数据中包含的更新规范，从高速缓存数据存储单元（14）或家用电器和服务器设备获取相应的元素数据，并生成管理屏幕。控制器（10）将生成的管理屏幕发送到终端设备并显示所述屏幕。

94. 发明申请

WO2014182393A1 MEMORY POWER SAVINGS IN IDLE DISPLAY CASE 审中-公开
标题翻译：空闲显示器中的存储器功率节省
公开(公告)号：WO2014182393A1
公开(公告)日：2014-11-13
申请号：PCT/US2014/032811
申请日：2014-04-03
申请人： APPLE INC.
发明人： SUKALPA, Biswas , SHIU, Shinye , DE LA CROPTE DE CHANTERAC, Cyril , GULATI, Manu , DESAI, Pulkit , HU, Rong Zhang
IPC分类号： G06F3/14 , G09G5/393 , G09G5/395 , G09G5/00
CPC分类号： G06F1/3275 , G06F1/3218 , G06F1/3287 , G06F3/14 , G06F12/0873 , G06F2212/455 , G09G5/001 , G09G5/393 , G09G5/395 , G09G2330/02 , G09G2330/021 , G09G2360/121
摘要： In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
摘要翻译：在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。

95. 发明公开

EP3404529A1 PROGRESSIVE CHART RENDERING 无效
公开(公告)号：EP3404529A1
公开(公告)日：2018-11-21
申请号：EP17002027.5
申请日：2017-12-13
申请人： SAP SE
发明人： Sekharan, Satishkumar , Wang, Yuru
IPC分类号： G06F3/14 , G06F17/22 , G06F17/30
CPC分类号： G06F17/30554 , G06F3/14 , G06F12/0875 , G06F17/30902 , G06F17/30905 , G06F2212/455 , G09G2360/121 , G09G2370/027
摘要： A system includes reception of a request to display a data chart. In response to the request, a cached version of the data chart is retrieved from a memory, the cached version of the data chart is displayed, and while the cached version of the data chart is displayed, current data of the data chart is requested from a remote data source. Also while the cached version of the data chart is displayed, an active version of the data chart is rendered based on the current data. The displayed cached version is then replaced with a display of the rendered active version.

96. 发明公开

EP3333715A1 CACHE SYSTEM AND METHOD FOR GENERATING UNCACHED OBJECTS FROM CACHED AND STORED OBJECT COMPONENTS 审中-公开
公开(公告)号：EP3333715A1
公开(公告)日：2018-06-13
申请号：EP18152715.1
申请日：2001-08-08
申请人： Aware, Inc.
发明人： Gut, Ron Abraham , Tzannes, Alexis Paul , Reiter, Edmund Campion
IPC分类号： G06F12/08 , G06F17/30 , G06T1/60 , G06F12/0802 , G06F12/0875
CPC分类号： G06T1/60 , G06F12/0802 , G06F12/0875 , G06F16/10 , G06F2212/455
摘要： Methods and apparatus for constructing objects within a cache system thereby allowing the cache system to respond to requested objects that are not initially available within the cache system. One embodiment of the invention caches image files, where the images are divided into components and stored in a format that allows identification and access to the components. The cache system determines that an object, such as an image file, is missing from the cache memory, locates sufficient components from the cache memory and/or external storage, and constructs the object from the located components.

97. 发明公开

EP3238117A1 INFORMATION PROCESSING SYSTEM, IMAGE PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM 审中-公开
标题翻译：信息处理系统，图像处理装置，信息处理方法和记录介质
公开(公告)号：EP3238117A1
公开(公告)日：2017-11-01
申请号：EP15872220.7
申请日：2015-12-16
申请人： Ricoh Company, Ltd.
发明人： NAGATA, Tadashi
IPC分类号： G06F21/45 , H04L29/06 , H04N1/00 , G06F3/00 , G06F11/00 , G06F21/57 , G06F21/31 , G06F21/60
CPC分类号： H04N1/4413 , G06F3/00 , G06F9/451 , G06F12/0802 , G06F21/31 , G06F21/575 , G06F21/608 , G06F2212/455 , G06F2212/60 , G06F2221/2145 , H04L63/0892 , H04N1/00 , H04N1/00244 , H04N1/4433 , H04N2201/0094
摘要： An information processing system includes a first storage that stores user information about one or more users of the information processing system; a second storage; a first determining unit that determines, depending on whether a program sets the second storage to store predetermined user information from the user information stored in the first storage, the predetermined user information being used in the program, whether to store the predetermined user information in the second storage; and a user information process unit that obtains the predetermined user information from the user information and stores the predetermined user information in the second storage if the first determining unit determines that the predetermined user information is to be stored in the second storage.
摘要翻译：信息处理系统包括：第一存储器，存储关于信息处理系统的一个或多个用户的用户信息; 第二存储器; 第一确定单元，其根据程序是否设置第二存储器来存储来自存储在第一存储器中的用户信息的预定用户信息，在程序中使用预定用户信息，确定是否将预定用户信息存储在第二存储; 以及用户信息处理单元，如果第一确定单元确定预定用户信息将被存储在第二存储装置中，则用户信息处理单元从用户信息中获得预定用户信息，并将预定用户信息存储在第二存储装置中。

98. 发明公开

EP3014456A1 PAGE MANAGEMENT APPROACH TO FULLY UTILIZE HARDWARE CACHES FOR TILED RENDERING 审中-公开
标题翻译： SEITENVERWALTUNGSANSATZ ZURVOLLSTÄNDIGENVERWENDUNG EINES HARDWARE-CACHESPEICHERSFÜRVERTEILTE DARSTELLUNG
公开(公告)号：EP3014456A1
公开(公告)日：2016-05-04
申请号：EP13888103.2
申请日：2013-06-24
申请人： Intel Corporation
发明人： KOKER, Altug , NAVALE, Aditya
IPC分类号： G06F12/08 , G06F3/14
CPC分类号： G06T1/60 , G06F12/0802 , G06F2212/455 , G09G5/363 , G09G5/393 , G09G2360/121 , G09G2360/122
摘要： Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.
摘要翻译：系统和方法可以提供用于识别与图像相关联的瓦片，并将瓦片的整体排列成与帧缓冲器相关联的页面的线性流。另外，可以将页面的线性流分配给高速缓存。在一个示例中，根据高速缓存的固定集合选择策略将页面的线性流分配给高速缓存。

99. 发明公开

EP2936492A1 MULTI-MODE MEMORY ACCESS TECHNIQUES FOR PERFORMING GRAPHICS PROCESSING UNIT-BASED MEMORY TRANSFER OPERATIONS 有权
标题翻译：多模式记忆具体实施方式存储器传输操作与图形处理单元
公开(公告)号：EP2936492A1
公开(公告)日：2015-10-28
申请号：EP13803357.6
申请日：2013-11-21
申请人： Qualcomm Incorporated
发明人： GRUBER, Andrew Evan , WANG, Tao , KHANDELWAL, Shambhoo
IPC分类号： G11C7/10 , G09G5/393 , G09G3/36 , G09G5/395 , G09F3/14 , G06F12/02 , G06F12/06 , G06F13/16
CPC分类号： G09G5/363 , G06F12/0607 , G06F12/0875 , G06F2212/1021 , G06F2212/455 , G06F2212/601 , G09G5/393 , G09G5/395
摘要： This disclosure describes techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.

100. 发明公开

EP2756485A1 ACCELERATED TEXTURE LOOKUPS USING TEXTURE COORDINATE DERIVATIVES 有权转让
标题翻译：加速结构研究使用纹理坐标衍生物
公开(公告)号：EP2756485A1
公开(公告)日：2014-07-23
申请号：EP12831782.3
申请日：2012-09-11
申请人： Sony Computer Entertainment Inc.
发明人： OSMAN, Steven
IPC分类号： G06T17/00 , G06T1/00
CPC分类号： G06T15/04 , G06F12/0207 , G06F12/0215 , G06F2212/455 , G06T15/005
摘要： Methods, systems, and devices are disclosed for preparing to prefetch memory in 3D graphical shader programs. Based on the memory addresses of texels from a texture map that were previously read, a memory address of a to-be-read texel is estimated by using a first-order derivative of the memory address with respect to pixel distance. The estimated memory address is then prefetched for use when the pixel corresponding to the texel is rendered. Whether or not to perform the estimation of the texel memory address can be determined by whether the corresponding pixels are on the same, flat facet on a 3D model. Multiple directions on the facet can be used for memory address estimation as well as higher-order derivatives.

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