专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明专利

JP2007059060A Method for recording signal for indicating set of signal data in cd-r disk, controller for recordable compact disk, and computer system 审中-公开
标题翻译：用于记录CD-R盘中信号数据集的信号记录方法，用于记录紧凑磁盘的控制器和计算机系统
公开(公告)号：JP2007059060A
公开(公告)日：2007-03-08
申请号：JP2006329950
申请日：2006-12-06
申请人： Cirrus Logic Inc , シーラスロジック,インコーポレイテッドCirrus Logic,Inc.
发明人： KATO KEISUKE
IPC分类号： G11B20/10 , G11B27/10 , G06F3/06 , G11B7/00 , G11B7/0045 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/034 , G11B27/36
CPC分类号： G06F3/0601 , G06F2003/0692 , G11B20/10 , G11B20/1426 , G11B20/1833 , G11B27/034 , G11B27/36 , G11B2220/213 , G11B2220/218 , G11B2220/2545
摘要： PROBLEM TO BE SOLVED: To provide a CD-R controller having a sufficient throughput performance and capable of generating a control signal at sufficient speed.
SOLUTION: The CD-R controller includes a buffer manager for receiving a command like a cue sheet, and sends the command to a micro-controller. The micro-controller generates instructions corresponding to each command by using information stored in a ROM. The buffer manager stores the instructions in a buffer and then sends the instructions to a CD-R formatter. The buffer manager then sends signal data corresponding to the instructions to a recording circuit. The CD-R formatter generates control signals to the recording circuit from the instructions. The control signals cause recording circuit to generate recording signals to a CD-R drive. The CD-R drive records the signal indicative of the signal data in response to the recording signals.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供具有足够的吞吐量性能并且能够以足够的速度产生控制信号的CD-R控制器。解决方案：CD-R控制器包括缓冲管理器，用于接收诸如提示表的命令，并将该命令发送到微控制器。微控制器通过使用存储在ROM中的信息来生成与每个命令相对应的指令。缓冲区管理器将指令存储在缓冲区中，然后将指令发送到CD-R格式化程序。然后，缓冲器管理器将对应于指令的信号数据发送到记录电路。 CD-R格式器从指令向记录电路生成控制信号。控制信号使记录电路产生到CD-R驱动器的记录信号。 CD-R驱动器响应于记录信号记录指示信号数据的信号。版权所有（C）2007，JPO＆INPIT

92. 发明专利

JP2007049745A Delta-sigma modulator with improved noise performance 有权
标题翻译：具有改进噪声性能的DELTA-SIGMA调制器
公开(公告)号：JP2007049745A
公开(公告)日：2007-02-22
申请号：JP2006282024
申请日：2006-10-16
申请人： Cirrus Logic Inc , シラスロジック、インコーポレイテッド
发明人： MELANSON JOHN LAURENCE , YANG YU QING
IPC分类号： H03M3/04 , H03M3/00
CPC分类号： H03M3/368 , H03M3/424 , H03M3/452
摘要： PROBLEM TO BE SOLVED: To provide improving techniques for reducing noise, in a delta-sigma modulator.
SOLUTION: An integrator stage for use in a delta-sigma modulator includes an operational amplifier (312), an integration capacitor (C
I ) coupling an output of the operational amplifier (312) and a summing node at an input of the operational amplifier, and a feedback path. The feedback path includes a first capacitor (+C
REF ) and a second capacitor (-C
REF ), having first plates coupled electrically, in common at a common plate node and switching circuitry (310a-310d) for sampling selected reference voltages onto the second plates of the capacitors during sampling phase. The integrator stage further includes a switch (305a, 305b) for selectively coupling the common plate node and the summing node during integration phase.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：在Δ-Σ调制器中提供用于降低噪声的改进技术。解调器：用于Δ-Σ调制器的积分器级包括运算放大器（312），耦合运算放大器（312）的输出的积分电容器（C I ）和运算放大器输入端的求和节点和反馈路径。反馈路径包括第一电容器（+ C REF ）和第二电容器（-C REF ），其中第一电容器在公共板节点处共同电耦合，开关电路（310a-310d），用于在采样阶段期间将选定的参考电压采样到电容器的第二板上。积分器级还包括用于在积分阶段期间选择性地耦合公共板节点和求和节点的开关（305a，305b）。版权所有（C）2007，JPO＆INPIT

93. 发明专利

JP2007006544A Noise shaper with shared and independent filters and multiple quantizers and data converters 审中-公开
公开(公告)号：JP2007006544A
公开(公告)日：2007-01-11
申请号：JP2006280761
申请日：2006-10-13
申请人： Cirrus Logic Inc , シーラスロジック,インコーポレイテッドCirrus Logic,Inc.
发明人： MELANSON JOHN LAURENCE
IPC分类号： H03M3/02 , H03M7/32 , H03M3/04 , H03M7/36
CPC分类号： H03M7/3006 , H03M3/35 , H03M3/42 , H03M3/452 , H03M7/302 , H03M7/3037
摘要： PROBLEM TO BE SOLVED: To provide techniques which address the problem of mismatch between data conversion elements in DACs and ADCs.
SOLUTION: The noise shaper includes first and second quantizers and first and second feedback paths each providing feedback from a corresponding quantizer output. A loop filter system implements a plurality of transfer functions including a first non-zero transfer function between the first feedback path and an input of the first quantizer, a second non-zero transfer function between the first feedback path and an input of the second quantizer, a third non-zero transfer function between the second feedback path and the input of the first quantizer and a fourth non-zero transfer between the second feedback path and the input of the second quantizer.
COPYRIGHT: (C)2007,JPO&INPIT

94. 发明专利

JP2007006543A Noise shaper with shared and independent filters and multiple quantizers and data converters 审中-公开
标题翻译：具有共享和独立过滤器和多个量化器和数据转换器的噪声形状
公开(公告)号：JP2007006543A
公开(公告)日：2007-01-11
申请号：JP2006280760
申请日：2006-10-13
申请人： Cirrus Logic Inc , シーラスロジック,インコーポレイテッドCirrus Logic,Inc.
发明人： MELANSON JOHN LAURENCE
IPC分类号： H03M3/02 , H03M3/04 , H03M7/32 , H03M7/36
CPC分类号： H03M7/3006 , H03M3/35 , H03M3/42 , H03M3/452 , H03M7/302 , H03M7/3037
摘要： PROBLEM TO BE SOLVED: To provide techniques which address the problem of mismatch between data conversion elements in DACs and ADCs.
SOLUTION: The noise shaper includes first and second quantizers and first and second feedback paths each providing feedback from a corresponding quantizer output. A loop filter system implements a plurality of transfer functions including a first non-zero transfer function between the first feedback path and an input of the first quantizer, a second non-zero transfer function between the first feedback path and an input of the second quantizer, a third non-zero transfer function between the second feedback path and the input of the first quantizer and a fourth non-zero transfer between the second feedback path and the input of the second quantizer.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供解决DAC和ADC中的数据转换元件之间不匹配问题的技术。解决方案：噪声整形器包括第一和第二量化器以及每个提供来自相应量化器输出的反馈的第一和第二反馈路径。环路滤波器系统实现多个传递函数，包括在第一反馈路径和第一量化器的输入之间的第一非零传递函数，第一反馈路径和第二量化器的输入之间的第二非零传递函数在所述第二反馈路径和所述第一量化器的输入之间的第三非零传递函数以及所述第二反馈路径和所述第二量化器的输入之间的第四非零传递。版权所有（C）2007，JPO＆INPIT

95. 发明专利

JP2006081165A Single ended switched capacitor circuit 审中-公开
标题翻译：单端开关电容电路
公开(公告)号：JP2006081165A
公开(公告)日：2006-03-23
申请号：JP2005227404
申请日：2005-08-05
申请人： Cirrus Logic Inc , シラスロジック、インコーポレイテッド
发明人： GABORIAU JOHANN G , WEISER JOSEPH J
IPC分类号： H03H19/00 , H03K5/08 , H03M1/08
CPC分类号： H03M1/08
摘要： PROBLEM TO BE SOLVED: To remove the effect of common mode noise in a single end non-differential switched capacitor circuit.
SOLUTION: The circuit creates a capacitance divider using sampling capacitors Cs to create a stable and a noise-free common mode voltage (Vcom) signal. Once created, this Vcom signal is coupled between large common mode capacities Ccom which are preferably located outside to further be controlled in their values. Thereafter, the voltage Vcom can be stabilized while data are disconnected. In this way, the Vcom signal is not provided to the circuit, but instead, cleanly generated within the circuit itself when needed. Thereafter, the generated Vcom signal is made parallel with an integration capacitor C1 to generate the non-differential output voltage Vout. Then, the sampling capacitors Cs are shorted to remove charge stored in them and the process is repeated.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：消除单端非差分开关电容电路中共模噪声的影响。
解决方案：该电路使用采样电容器Cs创建一个电容分压器，以产生稳定和无噪声的共模电压（Vcom）信号。一旦创建，该Vcom信号耦合在大型共模容量Ccom之间，优选位于外部，以进一步控制其值。此后，电压Vcom可以在数据断开时稳定。以这种方式，Vcom信号不提供给电路，而是在需要时在电路本身内干净地产生。此后，所生成的Vcom信号与积分电容器C1并联，以产生非差分输出电压Vout。然后，采样电容器Cs短路以除去其中存储的电荷，并重复该过程。版权所有（C）2006，JPO＆NCIPI

96. 发明专利

JP2005182998A Spectrum smoothing filter 审中-公开
标题翻译： SPECTRUM SMOOTHING FILTER
公开(公告)号：JP2005182998A
公开(公告)日：2005-07-07
申请号：JP2005000251
申请日：2005-01-04
申请人： Cirrus Logic Inc , シーラスロジック,インコーポレイテッドCirrus Logic,Inc.
发明人： BEHRENS RICHARD T , GLOVER NEAL , TRENT DUDLEY O , ARMSTRONG ALAN J , ZOOK CHRISTOPHER P , BLISS WILLIAM G
IPC分类号： G11B5/09 , G11B20/10 , H03H17/02 , H03H17/06 , H04B3/06
CPC分类号： H03H17/06 , G11B5/09 , G11B20/10009 , H03H17/02
摘要： PROBLEM TO BE SOLVED: To provide a filter for compensating discrete secondary pulse formed in association with a data stream of discrete main pulses produced from a data read from magnetic media.
SOLUTION: The filter's impulse response comprises a center coefficient with a side compensating coefficient for attenuating the secondary pulses when an input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter (378, 373, 375, 377, 390, 396, 451, 453, 455, 459) provides the two programmable delays using only one delay line (390).
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于补偿与从磁性介质读取的数据产生的离散主脉冲的数据流相关联形成的离散次级脉冲的滤波器。滤波器的脉冲响应包括具有侧补偿系数的中心系数，用于当输入信号与脉冲响应卷积时衰减二次脉冲。补偿系数的幅度和延迟可编程，并进行自适应调整，以优化给定环境的脉冲响应。在传统的FIR实施例中，使用两条延迟线来产生中心系数和侧面补偿系数之间的两个可编程延迟。在优选实施例中，IIR滤波器（378,373,375,377,390,396,451,453,455,459）仅使用一个延迟线（390）提供两个可编程延迟。版权所有（C）2005，JPO＆NCIPI

97. 发明专利

JPH11282702A Simultaneous generation of ecc error syndrome and crc verification syndrome in dvd storage device 审中-公开
标题翻译： ECC存储设备中ECC错误综合症和CRC验证综合症的同时发生
公开(公告)号：JPH11282702A
公开(公告)日：1999-10-15
申请号：JP32572598
申请日：1998-11-16
申请人： Cirrus Logic Inc , シーラスロジック,インコーポレイテッド
发明人： CHRISTOPHER ZOCK
IPC分类号： G06F11/10 , G11B20/18 , H03M13/00 , H03M13/15 , H03M13/29
CPC分类号： H03M13/093 , G11B20/18 , G11B20/1833 , H03M13/1515 , H03M13/29 , H03M13/2909
摘要： PROBLEM TO BE SOLVED: To avoid a waiting time that is related to access to a data buffer which is for nonrandomizing data before generating a CRC syndrome by performing CRC check of randomized data.
SOLUTION: Randomized data is subjected to CRC check. In this error correction processor, a data buffer 1 stores an ECC code word that is read from a disk storage medium. A syndrome buffer stores plural intermediate values which are used to a verification syndrome in each data sector. An ECC decoder generates an error syndrome which is for correcting an error an ECC code word in accordance with the ECC code word stored in the buffer 1. An error verifier 19 verifies the correction that is performed about the ECC code word by the ECC decoder in accordance with a verification redundancy signal.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：为了避免在通过执行随机数据的CRC校验来生成CRC校验子之前与用于非随机数据的数据缓冲器的访问有关的等待时间。解决方案：随机数据进行CRC校验。在该纠错处理器中，数据缓冲器1存储从盘存储介质读取的ECC码字。校正子缓冲器存储用于每个数据扇区中的验证综合征的多个中间值。 ECC解码器产生用于根据存储在缓冲器1中的ECC码字来校正ECC码字的错误的错误校正子。错误校验器19验证由ECC解码器执行的关于ECC码字的校正根据验证冗余信号。

98. 发明专利

JPH11282701A Ecc system for generating crc syndrome to random data in computer storage device 有权
标题翻译：用于在计算机存储设备中产生CRC同步到随机数据的ECC系统
公开(公告)号：JPH11282701A
公开(公告)日：1999-10-15
申请号：JP32462398
申请日：1998-11-16
申请人： Cirrus Logic Inc , シーラスロジック,インコーポレイテッド
发明人： CHRISTOPHER ZOCK
IPC分类号： G06F11/10 , G11B20/18 , H03M13/00 , H03M13/15 , H03M13/29
CPC分类号： H03M13/093 , G11B20/18 , G11B20/1833 , H03M13/1515 , H03M13/158 , H03M13/29 , H03M13/2909
摘要： PROBLEM TO BE SOLVED: To avoid a waiting time that is related to access to a data buffer which is for nonrandomizing data before generating a cyclic redundancy check(CRC) syndrome by performing CRC check of randomized data. SOLUTION: Randomized data is subjected to CRC check. In this error correction processor, an error checking and correction(ECC) decoder uses an ECC redundancy signal and corrects an error in the randomized data. A syndrome generator 17 responds to the randomized data and generates a verification syndrome. A correction verifier 19 compares the verification syndrome with prescribed value and verifies the effectiveness and completeness of correction to the randomized data. A nonrandomizer nonrandomizes the randomized data after the verifier 19 shows that correction of the randomized data is effective and complete.
摘要翻译：要解决的问题：通过执行随机数据的CRC校验，避免在生成循环冗余校验（CRC）综合征之前与用于非随机数据的数据缓冲器的访问相关的等待时间。解决方案：随机数据进行CRC校验。在该纠错处理器中，错误检查和校正（ECC）解码器使用ECC冗余信号并校正随机数据中的错误。综合征发生器17响应于随机数据并产生验证综合征。校正验证器19将验证综合征与规定值进行比较，并验证对随机数据的校正的有效性和完整性。在验证者19显示随机数据的校正是有效和完整的之后，非随机数不随机化数据。

99. 发明专利

JPH11249920A ECC SYSTEM USING DATA BUFFER FOR STORAGE OF CODE WORD DATA AND SYNDROME BUFFER FOR STORAGE OF ERROR SYNDROME 失效
公开(公告)号：JPH11249920A
公开(公告)日：1999-09-17
申请号：JP32461298
申请日：1998-11-16
申请人： CIRRUS LOGIC INC
发明人： CHRISTOPHER ZOCK
IPC分类号： G06F11/10 , G11B20/18 , H03M13/15 , H03M13/29
摘要： PROBLEM TO BE SOLVED: To provide an error correction processor where the wait time related to further buffer access for syndrome generation is shortened. SOLUTION: The error correction processor corrects an error in binary data read out from an optical disk recording medium, and binary data includes an ECC redundant symbol of a multi-dimensional error correction code and a C1/C2 redundant symbol of a cross interleave Reed Solomon code (CIRC). Further, it includes a C1/C2 decoder which uses C1/C2 redundancy to correct an error in binary data stored in a syndrome buffer, an ECC syndrome generator 17 which generates an error syndrome in response to the code word which is stored in a data buffer and includes a data symbol and the ECC redundant symbol, and an ECC error corrector 18 which uses one error syndrome taken out from the syndrome buffer to correct an error in the code word stored in the data buffer 1.

100. 发明专利

JPH10301648A OUTPUT CIRCUIT AND CHIP 失效
公开(公告)号：JPH10301648A
公开(公告)日：1998-11-13
申请号：JP35370397
申请日：1997-12-22
申请人： CIRRUS LOGIC INC
发明人： KASHMIRI ABDUAL , ASSAR MAHMUD
IPC分类号： H02J1/00 , G05F3/24 , H03K19/003 , H03K19/0185
摘要： PROBLEM TO BE SOLVED: To generate an output signal that has a relatively high voltage level from a chip which is manufactured in the process of a relatively low voltage level. SOLUTION: A control signal logic circuit 15 receives three V data signal from an internal logic circuit of a chip and generates a control signal as a function of the data signal. A pseudo-ground generating circuit 17 is connected to the control signal logic circuit and generates a pseudo-ground that exceeds zero V and an intermediate output signal as a function of the control signal generated by the control signal logic circuit. An output signal generating circuit 19 is connected to the pseudo-ground generating circuit and generates five V output signal as a function of the intermediate output signal generated by the pseudo-ground generating circuit. As a result of pseudo-ground generation, voltage difference that is exposed to a semiconductor device in an output circuit is always less than five V, prevents an oxide layer of the semiconductor of the output circuit from deteriorating in an early stage and does not invite early deterioration of the chip, and a three V process chip interfaces with a five V process device.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式