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91. 发明申请

US20160246600A1 EFFICIENT INSTRUCTION FUSION BY FUSING INSTRUCTIONS THAT FALL WITHIN A COUNTER-TRACKED AMOUNT OF CYCLES APART 审中-公开
标题翻译：通过在相当数量的循环中倒装的说明书进行有效的指导性融合
公开(公告)号：US20160246600A1
公开(公告)日：2016-08-25
申请号：US15143522
申请日：2016-04-30
申请人： Ido Ouziel , Lihu Rappoport , Robert Valentine , Ron Gabor , Pankaj Raghuvanshi
发明人： Ido Ouziel , Lihu Rappoport , Robert Valentine , Ron Gabor , Pankaj Raghuvanshi
IPC分类号： G06F9/30 , G06F13/40 , G06F12/08
CPC分类号： G06F9/3853 , G06F9/3016 , G06F9/3017 , G06F9/30196 , G06F9/3836 , G06F12/084 , G06F12/0875 , G06F13/4063 , G06F2212/452 , G06F2212/62 , Y02D10/14 , Y02D10/151
摘要： A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.
摘要翻译：一种在计算机系统内实现高效指令融合的技术。在一个实施例中，如果指令队列中的第一指令与第二指令可熔，则处理器逻辑延迟第二指令的处理阈值时间量。

92. 发明授权

US09354877B2 Systems, apparatuses, and methods for performing mask bit compression 有权
标题翻译：用于执行掩码位压缩的系统，设备和方法
公开(公告)号：US09354877B2
公开(公告)日：2016-05-31
申请号：US13992709
申请日：2011-12-23
申请人： Bret L. Toll , Robert Valentine , Jesus Corbal , Elmoustapha Ould-Ahmed-Vall , Mark J. Charney
发明人： Bret L. Toll , Robert Valentine , Jesus Corbal , Elmoustapha Ould-Ahmed-Vall , Mark J. Charney
IPC分类号： G06F9/22 , G06F9/30
CPC分类号： G06F9/30018 , G06F9/30025 , G06F9/30098 , G06F9/30181
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor mask bit compression in response to a single mask bit compression instruction that includes a source writemask register operand, a destination writemask register operand, and an opcode are described.
摘要翻译：描述了在计算机处理器中执行屏蔽位压缩的系统，装置和方法的实施例，其响应于包括源写入寄存器操作数，目的地写入寄存器操作数和操作码的单个掩码位压缩指令。

93. 发明授权

US09244687B2 Packed data operation mask comparison processors, methods, systems, and instructions 有权
标题翻译：打包数据操作掩码比较处理器，方法，系统和指令
公开(公告)号：US09244687B2
公开(公告)日：2016-01-26
申请号：US13977153
申请日：2011-12-29
申请人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
发明人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/30189 , G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30101 , G06F9/30145
摘要： Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.
摘要翻译：接收指示具有第一打包数据操作屏蔽位的第一打包数据操作掩码的打包数据操作掩码比较指令和具有第二打包数据操作掩码位的第二打包数据操作掩码。第一掩码的每个打包数据操作屏蔽位对应于相应位置的第二掩码的打包数据操作屏蔽位。将第一个掩码的每个打包数据操作屏蔽位的按位AND和第二个掩码的每个对应的打包数据操作掩码位的第一个值修改为第一个值为零。否则将第一个标志修改为第二个值。如果第二掩码的每个对应的打包数据操作屏蔽位的按位NOT的第一掩码的每个打包数据操作屏蔽位的按位AND为零，则将第二标志修改为第三值。否则将第二个标志修改为第四个值。

94. 发明授权

US09053025B2 Apparatus and method for fast failure handling of instructions 有权
标题翻译：快速故障处理指令的装置和方法
公开(公告)号：US09053025B2
公开(公告)日：2015-06-09
申请号：US13729931
申请日：2012-12-28
申请人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
发明人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , G06F9/38
CPC分类号： G06F11/0793 , G06F9/3842 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/076 , G06F11/0772 , G06F11/1438
摘要： A processor is described comprising: instruction failure logic to perform a plurality of operations in response to a detected instruction execution failure, the instruction failure logic to be used for instructions which have complex failure modes and which are expected to have a failure frequency above a threshold, wherein the operations include: detecting an instruction execution failure and determining a reason for the failure; storing failure data in a destination register to indicate the failure and to specify details associated with the failure; and allowing application program code to read the failure data and responsively take one or more actions responsive to the failure, wherein the instruction failure logic performs its operations without invocation of an exception handler or switching to a low level domain on a system which employs hierarchical protection domains.
摘要翻译：描述了一种处理器，包括：响应于检测到的指令执行失败执行多个操作的指令失败逻辑，用于具有复杂故障模式并且预期具有高于阈值的故障频率的指令的指令故障逻辑其中，所述操作包括：检测指令执行失败并确定所述故障的原因; 将故障数据存储在目的地寄存器中以指示故障并指定与故障相关的细节; 并且允许应用程序代码读取故障数据并且响应于故障响应地采取一个或多个动作，其中指令失败逻辑执行其操作而不调用异常处理程序或切换到采用分级保护的系统上的低级域域名

95. 发明申请

US20150113246A1 INSTRUCTION AND LOGIC TO PROVIDE CONVERSIONS BETWEEN A MASK REGISTER AND A GENERAL PURPOSE REGISTER OR MEMORY 审中-公开
标题翻译：指令和逻辑提供掩码寄存器与一般用途寄存器或存储器之间的转换
公开(公告)号：US20150113246A1
公开(公告)日：2015-04-23
申请号：US13977732
申请日：2011-11-25
申请人： Elmoustapha Ould-Ahmed-Vall , Jesus Corbal , Robert Valentine , Bret L. Toll , Mark J. Charney
发明人： Elmoustapha Ould-Ahmed-Vall , Jesus Corbal , Robert Valentine , Bret L. Toll , Mark J. Charney
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30032 , G06F9/30145 , G06F9/30185 , G06F9/3826 , G06F9/3877
摘要： Instructions and logic provide conversions between a mask register and a general purpose register or memory. Some embodiments, responsive to an instruction specifying: a destination operand, a mask length corresponding to a number of mask data fields, and a source operand; values are read from data fields in the source operand, corresponding to the specified mask length, and stored to corresponding data fields in the destination operand specified by the instruction, wherein one of the source or the destination operands is a mask register. Values indicative of masked vector elements may be stored to any data fields in the destination operand other than the number of data fields corresponding to the specified mask length. For some embodiments, the other one of the source or the destination operands may be a general purpose register or a memory location.
摘要翻译：指令和逻辑在掩码寄存器和通用寄存器或存储器之间提供转换。一些实施例，响应于指定目的地操作数，对应于多个掩码数据字段的掩码长度和源操作数的指令; 从源操作数的数据字段读取值，该数据字段对应于指定的掩码长度，并存储到由指令指定的目标操作数中的相应数据字段，其中源操作数或目标操作数中的一个是掩码寄存器。指示屏蔽矢量元素的值可以被存储到目的地操作数中除了对应于指定掩码长度的数据字段的数目之外的任何数据字段。对于一些实施例，源或目的地操作数中的另一个可以是通用寄存器或存储器位置。

96. 发明授权

US08972698B2 Vector conflict instructions 有权
标题翻译：向量冲突指令
公开(公告)号：US08972698B2
公开(公告)日：2015-03-03
申请号：US12976616
申请日：2010-12-22
申请人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
发明人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30043 , G06F9/3838
摘要： A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.
摘要翻译：描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

97. 发明申请

US20150039851A1 METHODS, APPARATUS, INSTRUCTIONS AND LOGIC TO PROVIDE VECTOR SUB-BYTE DECOMPRESSION FUNCTIONALITY 有权
标题翻译：方法，装置，说明和逻辑提供矢量子字节分解功能
公开(公告)号：US20150039851A1
公开(公告)日：2015-02-05
申请号：US13956347
申请日：2013-07-31
申请人： Tal Uliel , Elmoustapha Ould-Ahmed-Vall , Thomas Willhalm , Robert Valentine
发明人： Tal Uliel , Elmoustapha Ould-Ahmed-Vall , Thomas Willhalm , Robert Valentine
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30032 , G06F9/30098 , G06F9/30109 , G06F9/30112 , G06F9/3016 , G06F9/3889
摘要： Methods, apparatus, instructions and logic provide SIMD vector sub-byte decompression functionality. Embodiments include shuffling a first and second byte into the least significant portion of a first vector element, and a third and fourth byte into the most significant portion. Processing continues shuffling a fifth and sixth byte into the least significant portion of a second vector element, and a seventh and eighth byte into the most significant portion. Then by shifting the first vector element by a first shift count and the second vector element by a second shift count, sub-byte elements are aligned to the least significant bits of their respective bytes. Processors then shuffle a byte from each of the shifted vector elements' least significant portions into byte positions of a destination vector element, and from each of the shifted vector elements' most significant portions into byte positions of another destination vector element.
摘要翻译：方法，装置，指令和逻辑提供SIMD矢量子字节解压缩功能。实施例包括将第一和第二字节混洗到第一向量元素的最低有效部分中，以及将第三和第四字节混入最重要部分。处理继续将第五和第六字节洗牌到第二向量元素的最低有效部分，并将第七和第八字节重新排列到最高有效部分。然后，通过将第一移位计数和第二向量元素移位第二移位计数，将子字节元素与它们各自的字节的最低有效位对齐。然后，处理器将来自移位向量元素的最小有效部分的每一个的字节从目的地向量元素的字节位置以及从每个移位向量元素的最高有效部分转移到另一目的地向量元素的字节位置。

98. 发明申请

US20140289503A1 PACKED DATA OPERATION MASK COMPARISON PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权
标题翻译：包装数据操作掩码比较处理器，方法，系统和指令
公开(公告)号：US20140289503A1
公开(公告)日：2014-09-25
申请号：US13977153
申请日：2011-12-29
申请人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
发明人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30101 , G06F9/30145
摘要： Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.
摘要翻译：接收指示具有第一打包数据操作屏蔽位的第一打包数据操作掩码的打包数据操作掩码比较指令和具有第二打包数据操作掩码位的第二打包数据操作掩码。第一掩码的每个打包数据操作屏蔽位对应于相应位置的第二掩码的打包数据操作屏蔽位。将第一个掩码的每个打包数据操作屏蔽位的按位AND和第二个掩码的每个对应的打包数据操作掩码位的第一个值修改为第一个值为零。否则将第一个标志修改为第二个值。如果第二掩码的每个对应的打包数据操作屏蔽位的按位NOT的第一掩码的每个打包数据操作屏蔽位的按位AND为零，则将第二标志修改为第三值。否则将第二个标志修改为第四个值。

99. 发明申请

US20140189426A1 APPARATUS AND METHOD FOR FAST FAILURE HANDLING OF INSTRUCTIONS 有权
标题翻译：快速故障处理指令的装置和方法
公开(公告)号：US20140189426A1
公开(公告)日：2014-07-03
申请号：US13729931
申请日：2012-12-28
申请人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
发明人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F9/3842 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/076 , G06F11/0772 , G06F11/1438
摘要： A processor is described comprising: instruction failure logic to perform a plurality of operations in response to a detected instruction execution failure, the instruction failure logic to be used for instructions which have complex failure modes and which are expected to have a failure frequency above a threshold, wherein the operations include: detecting an instruction execution failure and determining a reason for the failure; storing failure data in a destination register to indicate the failure and to specify details associated with the failure; and allowing application program code to read the failure data and responsively take one or more actions responsive to the failure, wherein the instruction failure logic performs its operations without invocation of an exception handler or switching to a low level domain on a system which employs hierarchical protection domains.
摘要翻译：描述了一种处理器，包括：响应于检测到的指令执行失败执行多个操作的指令失败逻辑，用于具有复杂故障模式并且预期具有高于阈值的故障频率的指令的指令故障逻辑其中，所述操作包括：检测指令执行失败并确定所述故障的原因; 将故障数据存储在目的地寄存器中以指示故障并指定与故障相关的细节; 并且允许应用程序代码读取故障数据并且响应于故障响应地采取一个或多个动作，其中指令失败逻辑执行其操作而不调用异常处理程序或切换到采用分级保护的系统上的低级域域名

100. 发明申请

US20140189309A1 METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE PERMUTE CONTROLS WITH LEADING ZERO COUNT FUNCTIONALITY 有权
标题翻译：方法，设备，说明和逻辑提供带有领先零点功能的PTE控制
公开(公告)号：US20140189309A1
公开(公告)日：2014-07-03
申请号：US13731008
申请日：2012-12-29
申请人： Christopher J. Hughes , Mikhail Plotnikov , Andrey Naraikin , Robert Valentine
发明人： Christopher J. Hughes , Mikhail Plotnikov , Andrey Naraikin , Robert Valentine
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3834
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
摘要翻译：说明和逻辑提供带有零计数功能的SIMD置换控制。一些实施例包括具有多个数据字段的寄存器的处理器，每个数据字段用于存储第二多个位。目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储对于相应数据字段设置为零的最重要连续位数的计数。响应于对向量前导零计数指令进行解码，执行单元对寄存器中的每个数据字段计数设置为零的最高有效连续位的数目，并将计数存储在第一目的地寄存器的相应数据字段中。向量前导零计数指令可用于生成与该组置换控制一起使用的置换控制和完成掩码，以解决采集修改散射SIMD操作中的依赖关系。

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