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91. 发明申请

US20100038700A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20100038700A1
公开(公告)日：2010-02-18
申请号：US12580289
申请日：2009-10-16
申请人： Tsutomu OKAZAKI , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu OKAZAKI , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： H01L29/792
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
摘要翻译：半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极。第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分第一个方向第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

92. 发明授权

US07502257B2 Semiconductor device 有权
公开(公告)号：US07502257B2
公开(公告)日：2009-03-10
申请号：US11797164
申请日：2007-05-01
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： G11C11/34
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

93. 发明授权

US07447959B2 Semiconductor integrated circuit and a method of testing the same 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US07447959B2
公开(公告)日：2008-11-04
申请号：US11785537
申请日：2007-04-18
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Masahiko Kimura , Isao Nakamura
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Masahiko Kimura , Isao Nakamura
IPC分类号： G01R31/28 , G06K5/04
CPC分类号： G11C29/021 , G01R31/30 , G01R31/31703 , G01R31/31725 , G01R31/3187 , G06F11/24 , G11C16/04 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2029/5004
摘要： A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.
摘要翻译：其中可以容易地与其他LSI并行设置用于确定其本身产生的脉冲的电压或宽度的控制信息的半导体集成电路（LSI），并且可以容易地校正设置信息。从外部评估装置，将预期值的电压重叠地提供给具有CPU和闪速存储器的多个LSI。每个LSI包含比较电路，其比较期望的电压值和本身产生的升压电压。 CPU参考比较结果并优化用于改变升压电压的数据寄存器中的控制数据。 CPU控制比较电路和数据寄存器，并且以自完成方式进行修整，从而以并行方式容易地对多个LSI进行修整，并且总的测试时间减少。

94. 发明授权

US07414283B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07414283B2
公开(公告)日：2008-08-19
申请号：US11415129
申请日：2006-05-02
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

95. 发明申请

US20060209599A1 Nonvolatile semiconductor memory 有权
公开(公告)号：US20060209599A1
公开(公告)日：2006-09-21
申请号：US11438337
申请日：2006-05-23
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

96. 发明授权

US07092296B2 Nonvolatile semiconductor memory 有权
公开(公告)号：US07092296B2
公开(公告)日：2006-08-15
申请号：US11138290
申请日：2005-05-27
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

97. 发明申请

US20060044871A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20060044871A1
公开(公告)日：2006-03-02
申请号：US11195684
申请日：2005-08-03
申请人： Hiroyuki Tanikawa , Toshihiro Tanaka , Yutaka Shinagawa , Takashi Yamaki
发明人： Hiroyuki Tanikawa , Toshihiro Tanaka , Yutaka Shinagawa , Takashi Yamaki
IPC分类号： G11C16/06
CPC分类号： G11C16/344
摘要： The present invention is directed to realize both higher reading speed and assurance of the larger number of rewriting times for a nonvolatile memory. A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area for storing information in accordance with a threshold voltage which varies. One or plural conditions out of erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area is/are made different from that/those in the second nonvolatile memory area, speed of reading information stored in the first nonvolatile memory area is higher than that of reading information stored in the second nonvolatile memory area, and the assured number of rewriting times in the second nonvolatile memory area is larger than that in the first nonvolatile memory area.
摘要翻译：本发明旨在实现更高的读取速度和对非易失性存储器的更大数量的重写时间的保证。半导体集成电路具有第一非易失性存储区域和用于根据变化的阈值电压存储信息的第二非易失性存储区域。擦除验证存储器栅极电压，擦除验证确定存储器电流，写入验证确定存储器栅极电压，写入验证确定存储器电流，擦除电压，擦除电压施加时间，写入电压和写入电压施加时间中的一个或多个条件第一非易失性存储器区域与第二非易失性存储区域中的那些不同，第一非易失性存储区域中存储的读取信息的速度高于存储在第二非易失性存储区域中的读取信息的速度，并且确定的数量在第二非易失性存储器区域中的重写次数大于第一非易失性存储器区域中的重写时间。

98. 发明申请

US20060009601A1 Stereoregular polymer and monomer thereof and process for production of both 失效
标题翻译：立体定向聚合物及其单体及其制备方法
公开(公告)号：US20060009601A1
公开(公告)日：2006-01-12
申请号：US10513756
申请日：2003-05-08
申请人： Akikazu Matsumoto , Toshihiro Tanaka
发明人： Akikazu Matsumoto , Toshihiro Tanaka
IPC分类号： C08F20/20
CPC分类号： C08F2/48 , C07C67/11 , C07C69/602 , C07C69/65 , C08F36/14
摘要： An ester derivant having a crystal structure in which the molecules in two adjacent molecule planes are antiparallel is created from a carboxylic acid having carbon-carbon double bond and a compound having a functional group that can react to a carboxyl group of the carboxylic acid. The crystal of the ester derivant is then subjected to light irradiation or heating.
摘要翻译：由具有碳 - 碳双键的羧酸和具有能够与羧酸的羧基反应的官能团的化合物产生具有两相邻分子平面中的分子反平行的晶体结构的酯衍生物。然后将酯衍生物的晶体进行光照射或加热。

99. 发明授权

US06963507B2 Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory 有权
公开(公告)号：US06963507B2
公开(公告)日：2005-11-08
申请号：US10419228
申请日：2003-04-21
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
IPC分类号： G11C16/02 , G11C8/02 , G11C16/12 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/12 , G11C2216/14
摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

100. 发明授权

US06747895B2 Nonvolatile semiconductor memory, data deletion method of nonvolatile semiconductor memory, information processing apparatus and nonvolatile semiconductor memory system 失效
标题翻译：非易失性半导体存储器，非易失性半导体存储器的数据删除方法，信息处理装置和非易失性半导体存储器系统
公开(公告)号：US06747895B2
公开(公告)日：2004-06-08
申请号：US10083602
申请日：2002-02-27
申请人： Yukiko Umemoto , Toshihiro Tanaka , Hiroyuki Tanikawa , Yutaka Shinagawa
发明人： Yukiko Umemoto , Toshihiro Tanaka , Hiroyuki Tanikawa , Yutaka Shinagawa
IPC分类号： G11C1604
CPC分类号： G11C16/3445 , G11C8/12 , G11C16/16 , G11C2216/18
摘要： This inventing is intended to shorten data deletion time of a nonvolatile semiconductor memory such as a flash memory (EEPROM). When deleting data written to a memory cell MC0 among flash memory cells MC0 to MC2 formed on a semiconductor substrate PSUB through a separation region NiSO, a voltage of p type well PWL0 in which the memory cell MC0 is formed is raised to 10V and a voltage of the separation region NiSO is raised to 12V by using a voltage application unit different from a voltage application unit applying a voltage to the p type well PWL0. As a result, parasitic capacitances Ca1 and Ca2 generated between p type wells PWL1 and PWL2 in which the unselected memory cells MC1 and MC2 are formed and the separation region NiSO, respectively, and a parasitic capacitance Cb generated between the separation region NiSO and the semiconductor substrate PSUB are charged by the voltage application units. It is, therefore, possible to shorten time required to charge the parasitic capacitances and to shorten the deletion time.
摘要翻译：本发明旨在缩短诸如闪速存储器（EEPROM）的非易失性半导体存储器的数据删除时间。当通过分离区域NiSO删除在半导体衬底PSUB上形成的闪存单元MC0至MC2中写入存储单元MC0的数据时，形成存储单元MC0的p型阱PWL0的电压升高到10V，通过使用与向p型阱PWL0施加电压的电压施加单元不同的电压施加单元将NiSO升高到12V。结果，在形成未选择的存储单元MC1和MC2的p型阱PWL1和PWL2之间分别产生的寄生电容Ca1和Ca2分别与分离区NiSO和半导体之间产生的寄生电容Cb 基板PSUB由电压施加单元充电。因此，可以缩短为寄生电容充电所需的时间并缩短删除时间。

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