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    • 91. 发明授权
    • Mask programmable gate array base cell
    • 面罩可编程门阵列基座
    • US5275962A
    • 1994-01-04
    • US682805
    • 1991-04-08
    • Masashi Hashimoto
    • Masashi Hashimoto
    • H01L21/82H01L21/3205H01L23/528H01L27/118H01L21/265
    • H01L27/11807H01L23/528H01L2924/0002
    • A method of forming a semiconductor gate array structure on a semiconductor substrate comprises the steps of forming a plurality of moat regions 12 and 14 where each of the moat regions 12 and 14 includes a channel region 22 and 28 and an insulating layer formed over the channel region 22 and 28. The moat regions separated by an insulating region 16. A plurality of gates 30 are formed wherein each of said gates 30 includes a first portion 30a over one of said channel regions 22, a second portion 30b over a channel region 28 adjacent to said one of said channel regions, and a third portion 30c over the insulating region 116 between said one of said channel regions. The gates 30 are formed such that each channel region is beneath one gate. The third portion 30a of a selected number of the gates is then etched to form the desired gate configuration. Finally, an additional insulating layer 160 may be formed over the array and contact holes formed in the layer such that interconnects may be created to form the desired transistor devices. Multiple levels of interconnects may be used. Modifications and variations, as well as an illustrative fabrication method are also disclosed.
    • 在半导体衬底上形成半导体栅极阵列结构的方法包括以下步骤:形成多个护沟区域12和14,其中每个护环区域12和14包括沟道区域22和28以及形成在沟道上的绝缘层 区域22和28.由绝缘区域16隔开的护城河区域。形成多个门30,其中每个所述门30包括位于所述沟道区22之一上的第一部分30a,在沟道区28上方的第二部分30b 邻近所述通道区域之一,以及位于所述通道区域之间的绝缘区域116上的第三部分30c。 门30形成为使得每个沟道区域在一个栅极下方。 然后蚀刻选定数量的栅极的第三部分30a以形成所需的栅极配置。 最后,可以在阵列上形成附加的绝缘层160,并且形成在层中的接触孔,使得可以产生互连以形成期望的晶体管器件。 可以使用多级互连。 还公开了修改和变化以及说明性的制造方法。
    • 94. 发明授权
    • Capacitor-driven signal transmission circuit
    • 电容驱动信号传输电路
    • US5198699A
    • 1993-03-30
    • US638267
    • 1991-01-07
    • Masashi HashimotoOh-Kyong Kwon
    • Masashi HashimotoOh-Kyong Kwon
    • H03K17/16
    • H03K17/164H03K17/163
    • A transmission line driver circuit (10) includes a signal input (12). A first capacitor (28) stores a first voltage level corresponding to a first of two possible bit values of an input signal. A second capacitor (44) stores a second voltage level corresponding to a second of the possible bit values. First and second voltage supply sources (24, 42) are selectively and respectively coupled to the first and second capacitors (28, 44) for recharging these capacitors to their respective voltage levels. A transmission line (50) is coupled to an output of a switching circuit. The switching circuit is operable to couple the first capacitor (28) to the switching circuit output (34) in response to receiving an input signal of a first bit value. The switching circuit is further operable to couple the second capacitor (44) to the output (34) in response to receiving an input signal of a second bit value. The bit value is thereby propagated onto the transmission line (50).
    • 传输线驱动电路(10)包括信号输入端(12)。 第一电容器(28)存储与输入信号的两个可能位值中的第一个相对应的第一电压电平。 第二电容器(44)存储对应于第二可能位值的第二电压电平。 第一和第二电压源(24,42)选择性地并分别耦合到第一和第二电容器(28,44),以将这些电容器再次充电到它们各自的电压电平。 传输线(50)耦合到开关电路的输出端。 响应于接收到第一位值的输入信号,开关电路可操作以将第一电容器(28)耦合到开关电路输出(34)。 响应于接收到第二位值的输入信号,开关电路还可操作以将第二电容器(44)耦合到输出(34)。 因此,位值传播到传输线(50)上。
    • 97. 发明授权
    • High performance test head and method of making
    • 高性能测试头和制作方法
    • US5090118A
    • 1992-02-25
    • US560398
    • 1990-07-31
    • On-Kyong KwonMasashi HashimotoSatwinder Malhi
    • On-Kyong KwonMasashi HashimotoSatwinder Malhi
    • G01R1/073G01R31/28H01R12/04
    • G01R31/2886G01R1/0735Y10T29/49149Y10T29/49155
    • A high performance test head (18) communicates test signals between integrated circuit test pads and integrated circuit tester. Test head (18) comprises metal bumps (22) that electrically couple with test pads to communicate test signals between test pads and test circuitry. Planar foundation plate (30) provides structural support. Compliant material layer (26) associates with metal bumps (22) and compresses to assure positive contact between metal bumps (22) and test pads. Compliant material layer (26) is positioned between foundation plate (30) and metal bumps (22). Interconnection line (20) adjoins test head (18) to connect metal bumps (22) between test circuitry and integrated circuits. The present invention includes a method for high performance communication of test signals between test pads and test circuitry. The present invention further includes the method of applying semiconductor device fabrication techniques to produce a high performance test head (18).
    • 高性能测试头(18)在集成电路测试焊盘和集成电路测试仪之间通信测试信号。 测试头(18)包括与测试焊盘电耦合以在测试焊盘和测试电路之间传送测试信号的金属凸块(22)。 平面基础板(30)提供结构支撑。 合适的材料层(26)与金属凸块(22)相关并且压缩以确保金属凸块(22)和测试垫之间的正接触。 合适的材料层(26)位于基板(30)和金属凸块(22)之间。 互连线(20)邻接测试头(18)以在测试电路和集成电路之间连接金属凸块(22)。 本发明包括用于测试焊盘和测试电路之间的测试信号的高性能通信的方法。 本发明还包括施加半导体器件制造技术以产生高性能测试头(18)的方法。