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91. 发明授权

US07620781B2 Efficient Bloom filter 失效
标题翻译：高效布鲁姆过滤器
公开(公告)号：US07620781B2
公开(公告)日：2009-11-17
申请号：US11642314
申请日：2006-12-19
申请人： Mauricio Breternitz, Jr. , Youfeng Wu , Peter G. Sassone , Jeffrey P. Rupley, II , Wesley Attrot , Bryan Black
发明人： Mauricio Breternitz, Jr. , Youfeng Wu , Peter G. Sassone , Jeffrey P. Rupley, II , Wesley Attrot , Bryan Black
IPC分类号： G06F12/0026
CPC分类号： G06F12/0864 , Y10S707/99943
摘要： Implementation of a Bloom filter using multiple single-ported memory slices. A control value is combined with a hashed address value such that the resultant address value has the property that one, and only one, of the k memories or slices is selected for a given input value, a, for each bank. Collisions are thereby avoided and the multiple hash accesses for a given input value, a, may be performed concurrently. Other embodiments are also described and claimed.
摘要翻译：使用多个单端口存储器片的Bloom过滤器的实现。控制值与散列地址值组合，使得所得到的地址值具有对于每个存储体的给定输入值a选择k个存储器或片中仅一个且仅一个的属性。因此避免了冲突，并且可以同时执行给定输入值a的多个哈希访问。还描述和要求保护其他实施例。

92. 发明申请

US20090172644A1 SOFTWARE FLOW TRACKING USING MULTIPLE THREADS 有权
标题翻译：使用多个线程的软件流程跟踪
公开(公告)号：US20090172644A1
公开(公告)日：2009-07-02
申请号：US11965271
申请日：2007-12-27
申请人： Vijayanand Nagarajan , Ho-Seop Kim , Youfeng Wu , Rajiv Gupta
发明人： Vijayanand Nagarajan , Ho-Seop Kim , Youfeng Wu , Rajiv Gupta
IPC分类号： G06F9/44
CPC分类号： G06F21/566 , G06F8/33 , G06F11/3636
摘要： Methods, systems and machine readable media are disclosed for performing dynamic information flow tracking. One method includes executing operations of a program with a main thread, and tracking the main thread's execution of the operations of the program with a tracking thread. The method further includes updating, with the tracking thread, a taint value associated with the value of the main thread to reflect whether the value is tainted, and determining, with the tracking thread based upon the taint value, whether use of the value by the main thread violates a specific security policy.
摘要翻译：公开了用于执行动态信息流跟踪的方法，系统和机器可读介质。一种方法包括执行具有主线程的程序的操作，并且使用跟踪线程跟踪主线程对程序的操作的执行。该方法还包括利用跟踪线程来更新与主线程的值相关联的污点值，以反映该值是否被污染，并且基于该着色值确定跟踪线程是否使用该值主线程违反了特定的安全策略。

93. 发明授权

US07506217B2 Apparatus and method for software-based control flow checking for soft error detection to improve microprocessor reliability 有权
标题翻译：用于软件错误检测的软件控制流程检查的装置和方法，以提高微处理器的可靠性
公开(公告)号：US07506217B2
公开(公告)日：2009-03-17
申请号：US11325773
申请日：2005-12-30
申请人： Edson Borin , Cheng C. Wang , Youfeng Wu
发明人： Edson Borin , Cheng C. Wang , Youfeng Wu
IPC分类号： G06F11/00
CPC分类号： G06F11/1004
摘要： A method and apparatus for software-based control flow checking for soft error detection. In one embodiment, the method includes the instrumentation of one basic block of a target program to update a signature register with a successor basic block signature at an end of the basic block. In addition, the basic block is instrumented to verify that contents of the signature register match a basic block signature at a beginning of the basic block. In one embodiment, an instruction is inserted within the basic block to cause the signature register to store a predetermined value if the contents of the signature register match a basic block signature. In one embodiment, a basic block may be subdivided into a plurality of regions; each region is assigned a signature and instrumented to update the signature register at a beginning of each region. Other embodiments are described and claimed.
摘要翻译：一种用于软错误检测的基于软件的控制流程检查的方法和装置。在一个实施例中，该方法包括在基本块的结尾处对目标程序的一个基本块的仪表进行更新具有后继基本块签名的签名寄存器。另外，基本块被验证以验证签名寄存器的内容是否与基本块开头的基本块签名相匹配。在一个实施例中，如果签名寄存器的内容与基本块签名匹配，则在基本块内插入指令以使签名寄存器存储预定值。在一个实施例中，基本块可以被细分为多个区域; 每个区域都被分配一个签名，并在每个区域的开头进行检测以更新签名寄存器。描述和要求保护其他实施例。

94. 发明授权

US07467377B2 Methods and apparatus for compiler managed first cache bypassing 有权
标题翻译：编译器管理的第一个缓存绕过的方法和设备
公开(公告)号：US07467377B2
公开(公告)日：2008-12-16
申请号：US10278682
申请日：2002-10-22
申请人： Youfeng Wu , Li-Ling Chen
发明人： Youfeng Wu , Li-Ling Chen
IPC分类号： G06F9/45 , G06F12/00
CPC分类号： G06F12/0888 , G06F8/4442 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F12/0897
摘要： Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.
摘要翻译：公开了管理第一高速缓存的旁路的方法和装置。在一种这样的方法中，识别具有大于或等于预定阈值的预期等待时间的加载指令。然后进行请求以将所识别的加载指令调度为具有预定的延迟。然后安排软件程序。然后将与预定软件程序中的加载指令相关联的实际延迟与预定延迟进行比较。如果实际延迟大于或等于预定延迟，则加载指令被标记为绕过第一高速缓存。

95. 发明申请

US20080244538A1 Multi-core processor virtualization based on dynamic binary translation 审中-公开
标题翻译：基于动态二进制翻译的多核处理器虚拟化
公开(公告)号：US20080244538A1
公开(公告)日：2008-10-02
申请号：US11728347
申请日：2007-03-26
申请人： Sreekumar R. Nair , Youfeng Wu
发明人： Sreekumar R. Nair , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F9/45554
摘要： A processor virtualization abstracts the behavior of a processor instruction set architecture from an underlying micro-architecture implementation. It is capable of running any processor instruction set architecture compatible software on any micro-architecture implementation. A system wide dynamic binary translator translates source system programs to target programs and manages the execution of those target programs. It also provides the necessary and sufficient infrastructure requires to render multi-core processor virtualization.
摘要翻译：处理器虚拟化从基础微架构实现中抽象出处理器指令集架构的行为。它能够在任何微架构实现上运行任何处理器指令集架构兼容的软件。系统的动态二进制翻译器将源系统程序转换为目标程序，并管理这些目标程序的执行。它还提供了必要和足够的基础架构来呈现多核处理器虚拟化。

96. 发明申请

US20080162990A1 Compiler technique for efficient register checkpointing to support transaction roll-back 有权
标题翻译：编译器技术，用于高效的注册检查点支持事务回滚
公开(公告)号：US20080162990A1
公开(公告)日：2008-07-03
申请号：US11648486
申请日：2006-12-28
申请人： Cheng Wang , Youfeng Wu
发明人： Cheng Wang , Youfeng Wu
IPC分类号： G06F11/07
CPC分类号： G06F9/3863 , G06F9/3004 , G06F9/3834 , G06F11/1407
摘要： A method and apparatus for efficient register checkpointing is herein described. A transaction is detected in program code. A recovery block is inserted in the program code to perform recovery operations in response to an abort of the first transaction. A roll-back edge is potentially inserted from an abort point to the recovery block. A control flow edge is inserted from the recovery block to a entry point of the transaction. Checkpoint code is inserted before the entry point to backup live-in registers in backup storage elements and recovery code is inserted in the recovery block to restor the live-in registers from the backup storage elements in response to an abort of the transaction.
摘要翻译：这里描述用于有效的寄存器检查点的方法和装置。在程序代码中检测到事务。在程序代码中插入恢复块，以响应于第一个事务的中止来执行恢复操作。回退边缘可能从中止点插入到恢复块。将控制流程边缘从恢复块插入到事务的入口点。检查点代码被插入到备份存储元件中的备份实时寄存器的入口点之前，并且恢复代码被插入到恢复块中以便从备份存储元件恢复实时寄存器以响应中止事务。

97. 发明申请

US20080162885A1 Mechanism for software transactional memory commit/abort in unmanaged runtime environment 有权
标题翻译：在非托管运行时环境中软件事务内存提交/中止的机制
公开(公告)号：US20080162885A1
公开(公告)日：2008-07-03
申请号：US11648005
申请日：2006-12-28
申请人： Cheng Wang , Youfeng Wu , Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Cheng Wang , Youfeng Wu , Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3842 , G06F9/3863 , G06F9/466
摘要： A method and apparatus for ensuring integrity of transaction exit functions is herein described. Dead local data in a transaction is prevented from overwriting local variables associated with a transaction exit function. In a write-buffering Software Transactional Memory (STM) system, a commit function is associated with a private stack to store local variables to ensure write-back of local dead data in a write-buffer does not corrupt the commit function. Similarly, in a roll-back STM, an abort function is associated with a private stack to store local variables to ensure the roll-back of a program stack with local dead data from a write log does not corrupt the abort function. Alternatively, one stack may be used for the transaction including a first function and an exit function. Here, local dead variables are detected and prevented from overwriting local variables of the exit function.
摘要翻译：这里描述了用于确保交易退出功能的完整性的方法和装置。防止事务中的死地方数据覆盖与事务退出功能相关联的局部变量。在写缓冲软件事务内存（STM）系统中，提交函数与专用堆栈相关联，以存储局部变量，以确保写缓冲区中的本地死数据的写回不会损坏提交函数。类似地，在回滚STM中，中止功能与专用堆栈相关联以存储局部变量，以确保来自写入日志的本地死亡数据的程序堆栈的回滚不会破坏中止功能。或者，可以将一个堆栈用于包括第一功能和退出功能的交易。这里，检测并防止局部死变量覆盖退出函数的局部变量。

98. 发明申请

US20070240141A1 Performing dynamic information flow tracking 审中-公开
标题翻译：执行动态信息流跟踪
公开(公告)号：US20070240141A1
公开(公告)日：2007-10-11
申请号：US11394287
申请日：2006-03-30
申请人： Feng Qin , Cheng Wang , Ho-Seop Kim , Yuanyuan Zhou , Youfeng Wu
发明人： Feng Qin , Cheng Wang , Ho-Seop Kim , Yuanyuan Zhou , Youfeng Wu
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F21/16 , G06F8/52 , G06F2221/2101
摘要： In one embodiment, the present invention includes a method for instrumenting a code block with code to perform dynamic information flow tracking. Then during execution, it may be determined whether a pattern of input data to the code block has been previously received by the code block. If so, the code block may be executed, otherwise the instrumented code block may be executed. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于用代码执行动态信息流跟踪的代码块的检测方法。然后在执行期间，可以确定代码块先前是否接收到代码块的输入数据的模式。如果是这样，则可以执行代码块，否则可以执行检测的代码块。描述和要求保护其他实施例。

99. 发明申请

US20070174837A1 Apparatus and method for redundant software thread computation 有权
标题翻译：冗余软件线程计算的装置和方法
公开(公告)号：US20070174837A1
公开(公告)日：2007-07-26
申请号：US11325925
申请日：2005-12-30
申请人： Cheng Wang , Youfeng Wu
发明人： Cheng Wang , Youfeng Wu
IPC分类号： G06F9/46
CPC分类号： G06F9/544 , G06F11/1497
摘要： An apparatus and method for redundant software thread computation. In one embodiment, the method includes the replication of an application into two communicating threads, a leading thread and a trailing thread. In one embodiment, the trailing thread repeats computations performed by the leading thread to detect transient faults, referred to herein as “soft errors.” A first in, first out (FIFO) buffer of shared memory is reserved for passing data between the leading thread and the trailing thread. The FIFO buffer may include a buffer head variable to write data to the FIFO buffer and a buffer tail variable to read data from the FIFO buffer. In one embodiment, data passing between the leading thread data buffering is restricted according to a data unit size and thread synchronization between a leading thread and the trailing thread is limited to buffer overflow/underflow detection. Other embodiments are described and claimed.
摘要翻译：一种用于冗余软件线程计算的装置和方法。在一个实施例中，该方法包括将应用程序复制到两个通信线程，前导线程和后退线程中。在一个实施例中，尾线重复由前导线执行的检测瞬态故障的计算，这里称为“软错误”。保留共享内存的先进先出（FIFO）缓冲区，用于在前导线程和后线程之间传递数据。 FIFO缓冲器可以包括用于向FIFO缓冲器写入数据的缓冲器头变量和用于从FIFO缓冲器读取数据的缓冲器尾部变量。在一个实施例中，根据数据单元大小限制在前导线程数据缓冲之间传递的数据，并且前导线程和后退线程之间的线程同步被限制为缓冲器溢出/下溢检测。描述和要求保护其他实施例。

100. 发明授权

US07095342B1 Compressing microcode 有权
标题翻译：压缩微码
公开(公告)号：US07095342B1
公开(公告)日：2006-08-22
申请号：US11096152
申请日：2005-03-31
申请人： Herbert Hum , Mauricio Breternitz, Jr. , Youfeng Wu , Sangwook Kim
发明人： Herbert Hum , Mauricio Breternitz, Jr. , Youfeng Wu , Sangwook Kim
IPC分类号： H03M7/40
CPC分类号： H03M7/3084
摘要： In one embodiment, the present invention includes a method to compress data stored in a memory to reduce size and power consumption. The method includes segmenting each word of a code portion into multiple fields, forming tables having unique entries for each of the fields, and assigning a pointer to each of the unique entries in each of the tables. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种压缩存储在存储器中的数据以减小尺寸和功率消耗的方法。该方法包括将代码部分的每个字段分割成多个字段，形成具有用于每个字段的唯一条目的表，并且将指针分配给每个表中的每个唯一条目。描述和要求保护其他实施例。

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