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    • 92. 发明申请
    • SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING SYSTEM
    • 基板加工方法和基板加工系统
    • US20100009274A1
    • 2010-01-14
    • US12446289
    • 2007-11-14
    • Yuichi Yamamoto
    • Yuichi Yamamoto
    • G03F7/20G03B27/42
    • H01L21/0274H01L21/3086H01L21/3088Y10S414/135Y10S414/137
    • There is disclosed a substrate processing method by a multi-patterning technique, which comprises a lithography process and an etching process, each of the processes is performed to one substrate at least twice. The substrate processing method is performed by using a substrate processing system comprising a plurality of process units for performing respective steps of the lithography process. When a second lithography process is performed to a substrate, process unit(s) for performing one or more steps of the second lithography process to be used in the second lithography process is automatically selected based on the process history of the first lithography process in such a way that the process unit(s) to be used in the second lithography process is (are) identical to the processed unit(s) used in the first lithography process.
    • 公开了一种通过多图案化技术的衬底处理方法,其包括光刻工艺和蚀刻工艺,每个工艺至少进行两次到一个衬底。 基板处理方法通过使用包括用于执行光刻处理的各个步骤的多个处理单元的基板处理系统来执行。 当对基板执行第二光刻工艺时,根据第一光刻工艺的处理历史自动选择用于执行在第二光刻工艺中使用的第二光刻工艺的一个或多个步骤的处理单元 在第二光刻工艺中使用的处理单元与第一光刻工艺中使用的处理单元相同的方式。
    • 93. 发明申请
    • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    • 制造半导体器件的方法
    • US20090042348A1
    • 2009-02-12
    • US12182322
    • 2008-07-30
    • Yuichi Yamamoto
    • Yuichi Yamamoto
    • H01L21/8234
    • H01L21/823456H01L29/66545H01L29/7843
    • In the present invention, there is provided a method for manufacturing a semiconductor device that has on a semiconductor substrate first and second transistor groups having different operating voltages respectively, the first transistor group having a first gate electrode, the second transistor group having a second gate electrode, the method including the steps of: forming the silicide layer on the first gate electrode of the first transistor group after setting a height of the first gate electrode smaller than a height of a dummy gate electrode formed in a dummy gate part; and forming a gate forming trench by removing the dummy gate part after forming an interlayer insulating film that covers a silicide layer and planarizing a surface of the interlayer insulating film.
    • 在本发明中,提供了一种制造半导体器件的方法,该半导体器件在半导体衬底上具有分别具有不同工作电压的第一和第二晶体管组,第一晶体管组具有第一栅电极,第二晶体管组具有第二栅极 电极,该方法包括以下步骤:在将第一栅电极的高度设置为比形成在虚拟栅极部分中的虚设栅电极的高度之后,在第一晶体管组的第一栅电极上形成硅化物层; 以及在形成覆盖硅化物层并平面化层间绝缘膜的表面的层间绝缘膜之后,通过去除伪栅极部分来形成栅极形成沟槽。
    • 99. 发明授权
    • Particle beam accelerator
    • 粒子束加速器
    • US07332880B2
    • 2008-02-19
    • US11374182
    • 2006-03-14
    • Nobuhiko InaYuichi YamamotoTakahisa Nagayama
    • Nobuhiko InaYuichi YamamotoTakahisa Nagayama
    • H05H7/00
    • H05H15/00
    • The present invention provides a particle beam accelerator for accelerating charged particles along a traveling direction of the charged particles. The invention provides a particle beam accelerator, in which the charged particle beam deflected by spiral-shaped-deflecting electromagnet 3, is accelerated by an accelerating unit 5, the charged particle beam circulating in an annular vacuum passageway of a vacuum duct 1 a plurality of times differing in orbit. And gap 9 is formed in the accelerating unit 5 of the vacuum duct 1, and gap-constituting face of the vacuum duct 1 is formed to be perpendicular to each of the traveling directions of the charged particle beam orbiting on a first orbit and on a second orbit. In the above accelerator, vibrations of the charged particle beam can be brought under control and loss of the charged particle beam can be reduced.
    • 本发明提供一种用于沿带电粒子的行进方向加速带电粒子的粒子束加速器。 本发明提供了一种粒子束加速器,其中由螺旋形偏转电磁体3偏转的带电粒子束由加速单元5加速,带电粒子束在真空管道1的环形真空通道中循环多个 时间在轨道上不同。 并且,在真空管1的加速部5中形成有间隙9,真空管1的间隙构成面与第一轨道上的带电粒子束的行进方向垂直, 第二轨道 在上述加速器中,可以控制带电粒子束的振动,并且可以减少带电粒子束的损耗。