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91. 发明申请

US20050248906A1 Capacitor that includes high permittivity capacitor dielectric 有权
标题翻译：包括高介电常数电容器电容器的电容器
公开(公告)号：US20050248906A1
公开(公告)日：2005-11-10
申请号：US11167694
申请日：2005-06-27
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01G4/228 , H01L21/00 , H01L21/02 , H01L21/334 , H01L21/762 , H01L21/8239 , H01L21/84 , H01L27/00 , H01L27/105 , H01L27/108 , H01L27/12 , H01L29/92 , H01L29/94
CPC分类号： H01L27/0805 , H01L21/84 , H01L27/1203 , H01L28/55 , H01L28/65 , H01L29/66181 , H01L29/94 , Y10S257/905 , Y10S257/908
摘要： A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.
摘要翻译：在包括硅表面层的半导体衬底上形成去耦电容器。在半导体表面层的一部分中形成基本平坦的底部电极。电容器电介质覆盖在底部电极上。电容器电介质由具有相对介电常数（优选大于约5）的高介电常数电介质形成。电容器还包括覆盖在电容器电介质上的基本平坦的顶部电极。在优选的应用中，顶部电极连接到第一参考电压线，底部电极连接到第二参考电压线。

92. 发明授权

US06940705B2 Capacitor with enhanced performance and method of manufacture 有权
标题翻译：具有增强性能和制造方法的电容器
公开(公告)号：US06940705B2
公开(公告)日：2005-09-06
申请号：US10627218
申请日：2003-07-25
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/02 , H01L27/08 , H01L29/94 , H01G4/35
CPC分类号： H01L28/40 , H01L27/0805 , H01L29/94 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is formed in a semiconductor substrate that includes a strained silicon layer. A substantially flat bottom electrode is formed in a portion of the strained silicon layer and a capacitor dielectric overlying the bottom electrode. A substantially flat top electrode overlies said capacitor dielectric. The top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.
摘要翻译：在包括应变硅层的半导体衬底中形成去耦电容器。基本平坦的底部电极形成在应变硅层的一部分和覆盖底部电极的电容器电介质上。基本平坦的顶部电极覆盖所述电容器电介质。顶部电极连接到第一参考电压线，底部电极连接到第二参考电压线。

93. 发明申请

US20050036184A1 Lithography apparatus for manufacture of integrated circuits 有权
标题翻译：用于制造集成电路的光刻设备
公开(公告)号：US20050036184A1
公开(公告)日：2005-02-17
申请号：US10826602
申请日：2004-04-16
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： G03F7/20 , G02B5/32
CPC分类号： G03F7/70341
摘要： An immersion lithographic system 10 comprises an optical surface 51, an immersion fluid 60 contacting at least a portion of the optical surface, and a semiconductor structure 80 having a topmost photoresist layer 70 having a thickness of less than about 5000 angstroms, wherein a portion of the photoresist is in contact with the immersion fluid. Further, a method for illuminating a semiconductor structure 80 having a topmost photoresist layer 70 with a thickness of less than about 5000 angstroms, comprising introducing an immersion fluid 60 into a space between an optical surface 51 and the photoresist layer, and directing light preferably with a wavelength of less than about 450 nm through the immersion fluid and onto the photoresist.
摘要翻译：浸没式光刻系统10包括光学表面51，与光学表面的至少一部分接触的浸没流体60和具有小于约5000埃的厚度的最顶层光致抗蚀剂层70的半导体结构80，其中一部分光致抗蚀剂与浸没流体接触。此外，一种用于照射具有小于约5000埃的厚度的最上面的光致抗蚀剂层70的半导体结构80的方法，包括将浸没流体60引入到光学表面51和光致抗蚀剂层之间的空间中，并且优选地引导光波长小于约450nm，通过浸没流体和光致抗蚀剂。

94. 发明申请

US20050035369A1 Structure and method of forming integrated circuits utilizing strained channel transistors 审中-公开
标题翻译：使用应变通道晶体管形成集成电路的结构和方法
公开(公告)号：US20050035369A1
公开(公告)日：2005-02-17
申请号：US10729092
申请日：2003-12-05
申请人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chenming Hu
发明人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/11 , H01L29/78 , H01L31/0328
CPC分类号： H01L29/6653 , H01L21/823807 , H01L21/823814 , H01L27/1104 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7842 , H01L29/7848
摘要： A semiconductor device or circuit is formed on a semiconductor substrate with first and second semiconductor materials having different lattice-constants. A first transistor includes a channel region formed oppositely adjacent a source and drain region. At least a portion of the source and drain regions are formed in the second semiconductor material thereby forming lattice-mismatched zones in the first transistor. A second component is coupled to the transistor to form a circuit, e.g., an inverter. The second component can be a second transistor having a conductivity type differing from the first transistor or a resistor.
摘要翻译：半导体器件或电路在具有不同晶格常数的第一和第二半导体材料的半导体衬底上形成。第一晶体管包括与源区和漏区相对地形成的沟道区。源区和漏区的至少一部分形成在第二半导体材料中，从而在第一晶体管中形成晶格失配区。第二分量耦合到晶体管以形成电路，例如逆变器。第二部件可以是具有不同于第一晶体管或电阻器的导电类型的第二晶体管。

95. 发明申请

US20050018380A1 Capacitor with enhanced performance and method of manufacture 有权
公开(公告)号：US20050018380A1
公开(公告)日：2005-01-27
申请号：US10627218
申请日：2003-07-25
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/02 , H01L27/08 , H01L29/94 , H01G4/228
CPC分类号： H01L28/40 , H01L27/0805 , H01L29/94 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is formed in a semiconductor substrate that includes a strained silicon layer. A substantially flat bottom electrode is formed in a portion of the strained silicon layer and a capacitor dielectric overlying the bottom electrode. A substantially flat top electrode overlies said capacitor dielectric. The top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

96. 发明申请

US20050017286A1 Capacitor with improved capacitance density and method of manufacture 有权
标题翻译：具有改善电容密度的电容器和制造方法
公开(公告)号：US20050017286A1
公开(公告)日：2005-01-27
申请号：US10628020
申请日：2003-07-25
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01G4/228 , H01L21/00 , H01L21/02 , H01L21/334 , H01L21/762 , H01L21/8239 , H01L21/84 , H01L27/00 , H01L27/105 , H01L27/108 , H01L27/12 , H01L29/92 , H01L29/94
CPC分类号： H01L27/0805 , H01L21/84 , H01L27/1203 , H01L28/55 , H01L28/65 , H01L29/66181 , H01L29/94 , Y10S257/905 , Y10S257/908
摘要： A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.
摘要翻译：在包括硅表面层的半导体衬底上形成去耦电容器。在半导体表面层的一部分中形成基本平坦的底部电极。电容器电介质覆盖在底部电极上。电容器电介质由具有相对介电常数（优选大于约5）的高介电常数电介质形成。电容器还包括覆盖在电容器电介质上的基本平坦的顶部电极。在优选的应用中，顶部电极连接到第一参考电压线，底部电极连接到第二参考电压线。

97. 发明申请

US20160240372A9 Cobalt silicidation process for substrates comprised with a silicon-germanium layer 有权
标题翻译：用硅 - 锗层构成的衬底的硅化硅工艺
公开(公告)号：US20160240372A9
公开(公告)日：2016-08-18
申请号：US11714416
申请日：2007-03-06
申请人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L29/76
CPC分类号： H01L29/1054 , H01L21/02142 , H01L21/265 , H01L21/28052 , H01L21/28518 , H01L21/28525 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/7834
摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.
摘要翻译：一种方法包括在半导体衬底上提供半导体合金层，在半导体合金层上形成栅极结构，在半导体衬底的栅极结构的两侧形成源区和漏极区，去除半导体合金层的至少一部分覆盖源极和漏极区域，并且在源极和漏极区域上形成金属硅化物区域。

98. 发明授权

US08062946B2 Strained channel transistor structure with lattice-mismatched zone and fabrication method thereof 有权
标题翻译：具有晶格失配区的应变通道晶体管结构及其制造方法
公开(公告)号：US08062946B2
公开(公告)日：2011-11-22
申请号：US11093847
申请日：2005-03-30
申请人： Yee-Chia Yeo , Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu
发明人： Yee-Chia Yeo , Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/165 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7842 , H01L29/7848
摘要： A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.
摘要翻译：具有晶格失配区的应变通道晶体管结构及其制造方法。晶体管结构包括具有应变沟道区的衬底，包括表面上具有第一自然晶格常数的第一半导体材料，覆盖在应变沟道区上的栅极电介质层，覆盖栅极电介质层的栅电极和源极区域和漏极区域相邻地邻近应变通道区域，其中源区域和漏极区域中的一个或两个包括晶格失配区域，其包含具有不同于第一自然晶格常数的第二自然晶格常数的第二半导体材料。

99. 发明授权

US07202122B2 Cobalt silicidation process for substrates with a silicon—germanium layer 有权
标题翻译：具有硅 - 锗层的衬底的钴硅化工艺
公开(公告)号：US07202122B2
公开(公告)日：2007-04-10
申请号：US10710012
申请日：2004-06-11
申请人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/1054 , H01L29/665 , H01L29/66545 , Y10S438/933
摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.
摘要翻译：一种方法包括在半导体衬底上提供半导体合金层，在半导体合金层上形成栅极结构，在半导体衬底的栅极结构的两侧形成源区和漏极区，去除半导体合金层的至少一部分覆盖源极和漏极区域，并且在源极和漏极区域上形成金属硅化物区域。

100. 发明授权

US07183593B2 Heterostructure resistor and method of forming the same 有权
标题翻译：异质结构电阻及其形成方法
公开(公告)号：US07183593B2
公开(公告)日：2007-02-27
申请号：US10745831
申请日：2003-12-24
申请人： Yee-Chia Yeo , Wen-Chin Lee , Chih-Hsin Ko , Chung-Hu Ge , Chun-Chieh Lin , Chenming Hu
发明人： Yee-Chia Yeo , Wen-Chin Lee , Chih-Hsin Ko , Chung-Hu Ge , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L29/86 , H01L29/205
CPC分类号： H01L27/0629 , H01L29/165 , H01L29/8605
摘要： A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.
摘要翻译：异质结构电阻器包括形成在半导体衬底的一部分中的掺杂区域，该衬底包括具有第一自然晶格常数的第一半导体材料。掺杂区域包括覆盖半导体衬底的半导体层。半导体层包括具有第二自然晶格常数的第二半导体材料。

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