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91. 发明授权

US08560930B2 Systems and methods for multi-level quasi-cyclic low density parity check codes 有权
标题翻译：多级准循环低密度奇偶校验码的系统和方法
公开(公告)号：US08560930B2
公开(公告)日：2013-10-15
申请号：US13316858
申请日：2011-12-12
申请人： Zongwang Li , Chung-Li Wang , Lei Chen , Shaohua Yang
发明人： Zongwang Li , Chung-Li Wang , Lei Chen , Shaohua Yang
IPC分类号： H03M13/03
CPC分类号： H03M13/036 , H03M13/1142 , H03M13/116
摘要： Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: Various embodiments of the present invention provide methods for generating a code format. Such methods include: receiving an indication of a low weight codeword having a trapping set; selecting an initial value for a base matrix; testing the low weight codeword after modification by the initial value to determine an updated weight of the low weight codeword; and testing the low weight codeword after modification by the initial value to determine whether the trapping set remains.
摘要翻译：本发明的各种实施例提供了用于生成代码格式的系统和方法。所讨论的一种方法包括：本发明的各种实施例提供了用于生成代码格式的方法。这样的方法包括：接收具有陷阱集的低权重码字的指示; 选择基本矩阵的初始值; 通过初始值测试修改后的低权重码字以确定低权重码字的更新权重; 并通过初始值测试修改后的低权重码字，以确定捕获集是否保留。

92. 发明授权

US08250431B2 Systems and methods for phase dependent data detection in iterative decoding 有权
标题翻译：迭代解码中相位数据检测的系统和方法
公开(公告)号：US08250431B2
公开(公告)日：2012-08-21
申请号：US12512235
申请日：2009-07-30
申请人： Shaohua Yang , Zongwang Li , Weijun Tan , Kelly Fitzpatrick
发明人： Shaohua Yang , Zongwang Li , Weijun Tan , Kelly Fitzpatrick
IPC分类号： H03M13/00
CPC分类号： G11B20/1803 , G11B20/10222 , G11B2020/10722 , G11B2020/10759 , G11B2020/1287 , G11B2020/1289 , G11B2020/185 , H03M13/1105 , H03M13/27 , H03M13/2732 , H03M13/3905 , H03M13/4146 , H03M13/458 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output. A second detection circuit applies a phase dependent data detection algorithm to the phase shifted output such that a second output of the second data detection circuit varies from the first output at least in part due to a different phase of the data set presented to the second data detection circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种数据处理电路，其包括第一数据检测电路，该第一数据检测电路将相关数据检测算法应用于数据组，使得第一数据检测电路的第一输出根据所呈现的数据集的相位而变化第一数据检测电路。将数据集的第一阶段呈现给第一数据检测电路。这些电路还包括对第一输出应用解码算法以产生解码输出的解码器电路，以及相位移动电路，使得解码输出相移，使得提供数据组的第二相作为相移输出。第二检测电路将相位相关数据检测算法应用于相移输出，使得第二数据检测电路的第二输出至少部分地由于呈现给第二数据的数据集的相位而从第一输出变化检测电路。

93. 发明申请

US20110167246A1 Systems and Methods for Data Detection Including Dynamic Scaling 有权
标题翻译：包括动态缩放的数据检测系统和方法
公开(公告)号：US20110167246A1
公开(公告)日：2011-07-07
申请号：US12651547
申请日：2010-01-04
申请人： Shaohua Yang , Weijun Tan , Zongwang Li , Kiran Gunnam
发明人： Shaohua Yang , Weijun Tan , Zongwang Li , Kiran Gunnam
IPC分类号： G06F9/38
CPC分类号： H03M13/1105 , H03M13/2957 , H03M13/3961 , H03M13/6325 , H03M13/658 , H04L1/005 , H04L1/0057
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a channel detector circuit. The channel detector circuit includes a branch metric calculator circuit that is operable to receive a number of violated checks from a preceding stage, and to scale an intrinsic branch metric using a scalar selected based at least in part on the number of violated checks to yield a scaled intrinsic branch metric.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种包括信道检测器电路的数据处理系统。信道检测器电路包括分支度量计算器电路，其可操作以从前一级接收多个违反的检查，并且使用至少部分地基于违反检查的数量选择的标量来缩放固有分支度量，以产生缩放的内在分支度量。

94. 发明授权

US08683306B2 Systems and methods for data detection including dynamic scaling 有权
标题翻译：用于数据检测的系统和方法，包括动态缩放
公开(公告)号：US08683306B2
公开(公告)日：2014-03-25
申请号：US12651547
申请日：2010-01-04
申请人： Shaohua Yang , Weijun Tan , Zongwang Li , Kiran Gunnam
发明人： Shaohua Yang , Weijun Tan , Zongwang Li , Kiran Gunnam
IPC分类号： H03M13/03
CPC分类号： H03M13/1105 , H03M13/2957 , H03M13/3961 , H03M13/6325 , H03M13/658 , H04L1/005 , H04L1/0057
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a channel detector circuit. The channel detector circuit includes a branch metric calculator circuit that is operable to receive a number of violated checks from a preceding stage, and to scale an intrinsic branch metric using a scalar selected based at least in part on the number of violated checks to yield a scaled intrinsic branch metric.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种包括信道检测器电路的数据处理系统。信道检测器电路包括分支度量计算器电路，其可操作以从前一级接收多个违反的检查，并且使用至少部分地基于违反检查的数量选择的标量来缩放固有分支度量，以产生缩放的内在分支度量。

95. 发明授权

US08531320B2 Systems and methods for memory efficient data decoding 有权
标题翻译：用于存储器高效数据解码的系统和方法
公开(公告)号：US08531320B2
公开(公告)日：2013-09-10
申请号：US13295150
申请日：2011-11-14
申请人： Zongwang Li , Chung-Li Yang , Shaohua Yang , Changyou Xu
发明人： Zongwang Li , Chung-Li Yang , Shaohua Yang , Changyou Xu
IPC分类号： H03M7/00
CPC分类号： H03M7/30 , H03M7/6005
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a data decoder circuit. The data decoder circuit is operable to: apply a decoding algorithm to a decoder input on a first decoder iteration to yield a first decoder output; compress an output derived from the first decoder output to yield a compressed decoder output; de-compress the compressed decoder output to yield a second decoder output; and apply the decoding algorithm to the second decoder output to yield a third decoder output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种包括数据解码器电路的数据处理系统。数据解码器电路可操作以：在第一解码器迭代中将解码算法应用于解码器输入以产生第一解码器输出; 压缩从第一解码器输出得到的输出以产生压缩的解码器输出; 解压缩压缩解码器输出以产生第二解码器输出; 并将解码算法应用于第二解码器输出以产生第三解码器输出。

96. 发明申请

US20130120167A1 Systems and Methods for Memory Efficient Data Decoding 有权
标题翻译：高效数据解码的系统和方法
公开(公告)号：US20130120167A1
公开(公告)日：2013-05-16
申请号：US13295150
申请日：2011-11-14
申请人： Zongwang Li , Chung-Li Yang , Shaohua Yang , Changyou Xu
发明人： Zongwang Li , Chung-Li Yang , Shaohua Yang , Changyou Xu
IPC分类号： H03M7/30
CPC分类号： H03M7/30 , H03M7/6005
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a data decoder circuit. The data decoder circuit is operable to: apply a decoding algorithm to a decoder input on a first decoder iteration to yield a first decoder output; compress an output derived from the first decoder output to yield a compressed decoder output; de-compress the compressed decoder output to yield a second decoder output; and apply the decoding algorithm to the second decoder output to yield a third decoder output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种包括数据解码器电路的数据处理系统。数据解码器电路可操作以：在第一解码器迭代中将解码算法应用于解码器输入以产生第一解码器输出; 压缩从第一解码器输出得到的输出以产生压缩的解码器输出; 解压缩压缩解码器输出以产生第二解码器输出; 并将解码算法应用于第二解码器输出以产生第三解码器输出。

97. 发明申请

US20120033320A1 Systems and Methods for Dynamic Scaling in a Read Data Processing System 有权
标题翻译：读取数据处理系统中动态缩放的系统和方法
公开(公告)号：US20120033320A1
公开(公告)日：2012-02-09
申请号：US13126748
申请日：2009-04-28
申请人： Weijun Tan , Shaohua Yang , Kelly Fitzpatrick , Zongwang Li , Hao Zhong
发明人： Weijun Tan , Shaohua Yang , Kelly Fitzpatrick , Zongwang Li , Hao Zhong
IPC分类号： G11B20/10 , G06F11/07 , G06F7/00
CPC分类号： G11B20/1803 , G11B20/10222 , G11B2020/10722 , G11B2020/10759 , G11B2020/1287 , G11B2020/1289 , G11B2020/185 , H03M13/1111 , H03M13/112 , H03M13/2957 , H03M13/3746 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first dynamic scaling value and a second dynamic scaling value based at least in part on the decoded output. A first multiplier circuit multiplies the decoded output by the first dynamic scaling value and provides a first scaled output. A detector circuit receives the first scaled output and provides a detected output. A second multiplier circuit multiplies the detected output by the second dynamic scaling value and provides a second scaled output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括提供解码输出的解码器电路的数据处理系统，以及至少部分地基于解码输出来确定第一动态缩放值和第二动态缩放值的动态标量计算电路。第一乘法器电路将解码输出乘以第一动态缩放值并提供第一缩放输出。检测器电路接收第一缩放输出并提供检测输出。第二乘法器电路将检测到的输出乘以第二动态缩放值，并提供第二缩放输出。

98. 发明授权

US08443249B2 Systems and methods for low density parity check data encoding 有权
标题翻译：用于低密度奇偶校验数据编码的系统和方法
公开(公告)号：US08443249B2
公开(公告)日：2013-05-14
申请号：US12767761
申请日：2010-04-26
申请人： Zongwang Li , Kiran Gunnam , Shaohua Yang
发明人： Zongwang Li , Kiran Gunnam , Shaohua Yang
IPC分类号： H03M13/00
CPC分类号： H03M13/118 , H03M13/116 , H03M13/611
摘要： Various embodiments of the present invention provide systems and methods for encoding data. As an example, a data encoding circuit is disclosed that includes a first stage data encoder circuit and a second stage data encoder circuit. The first stage data encoder circuit is operable to provide a first stage output. The first stage data encoder circuit includes a first vector multiplier circuit operable to receive a data input and to multiply the data input by a first sparse matrix to yield a first interim value. The second stage encoder circuit includes a second vector multiplier circuit operable to multiply the first stage output by a second sparse matrix to yield a second interim value.
摘要翻译：本发明的各种实施例提供了用于编码数据的系统和方法。作为示例，公开了包括第一级数据编码器电路和第二级数据编码器电路的数据编码电路。第一级数据编码器电路可操作以提供第一级输出。第一级数据编码器电路包括第一向量乘法器电路，其可操作以接收数据输入，并将输入的数据乘以第一稀疏矩阵以产生第一临时值。第二级编码器电路包括第二矢量乘法器电路，其可操作以将第一级输出乘以第二稀疏矩阵以产生第二中间值。

99. 发明申请

US20130019141A1 Min-Sum Based Non-Binary LDPC Decoder 有权
标题翻译：基于最小和非二进制LDPC解码器
公开(公告)号：US20130019141A1
公开(公告)日：2013-01-17
申请号：US13180495
申请日：2011-07-11
申请人： Chung-Li Wang , Zongwang LI , Shaohua Yang
发明人： Chung-Li Wang , Zongwang LI , Shaohua Yang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1148 , H03M13/1117 , H03M13/1171 , H03M13/6583
摘要： Various embodiments of the present invention provide systems and methods for min-sum based decoding of non-binary LDPC codes. For example, a non-binary low density parity check data decoding system is discussed that includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node message vectors and to calculate perceived values based on check node to variable node message vectors. The check node processor is operable to generate the check node to variable node message vectors and to calculate checksums based on variable node to check node message vectors. The check node processor includes a minimum and subminimum finder circuit operable to process a plurality of sub-messages in each variable node to check node message vector. The check node processor also includes a select and combine circuit operable to combine an output of the minimum and subminimum finder circuit to generate the check node to variable node message vectors.
摘要翻译：本发明的各种实施例提供了用于非二进制LDPC码的基于最小和解码的系统和方法。例如，讨论了包括可变节点处理器和校验节点处理器的非二进制低密度奇偶校验数据解码系统。可变节点处理器可操作以生成可变节点以检查节点消息向量并且基于校验节点到可变节点消息向量来计算感知值。校验节点处理器可用于将校验节点生成到可变节点消息向量，并且基于变量节点来计算校验和以校验节点消息向量。校验节点处理器包括可操作以处理每个变量节点中的多个子消息以检查节点消息向量的最小和最小取景器电路。校验节点处理器还包括可操作以组合最小和最小取景器电路的输出的选择和组合电路，以生成可变节点消息向量的校验节点。

100. 发明申请

US20120089888A1 Systems and Methods for Multi-Level Quasi-Cyclic Low Density Parity Check Codes 有权
标题翻译：多级准循环低密度奇偶校验码系统与方法
公开(公告)号：US20120089888A1
公开(公告)日：2012-04-12
申请号：US13316858
申请日：2011-12-12
申请人： Zongwang Li , Chung-Li Wang , Lei Chen , Shaohua Yang
发明人： Zongwang Li , Chung-Li Wang , Lei Chen , Shaohua Yang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/036 , H03M13/1142 , H03M13/116
摘要： Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: Various embodiments of the present invention provide methods for generating a code format. Such methods include: receiving an indication of a low weight codeword having a trapping set; selecting an initial value for a base matrix; testing the low weight codeword after modification by the initial value to determine an updated weight of the low weight codeword; and testing the low weight codeword after modification by the initial value to determine whether the trapping set remains.
摘要翻译：本发明的各种实施例提供了用于生成代码格式的系统和方法。所讨论的一种方法包括：本发明的各种实施例提供了用于生成代码格式的方法。这样的方法包括：接收具有陷阱集的低权重码字的指示; 选择基本矩阵的初始值; 通过初始值测试修改后的低权重码字以确定低权重码字的更新权重; 并通过初始值测试修改后的低权重码字，以确定捕获集是否保留。

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