专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US08607129B2 Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic 有权
公开(公告)号：US08607129B2
公开(公告)日：2013-12-10
申请号：US13175500
申请日：2011-07-01
申请人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
发明人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
IPC分类号： H03M13/00 , G06F11/10
CPC分类号： G06F11/10 , G06F11/1076 , H03M1/1052 , H03M7/42 , H03M13/09 , H03M13/091 , H03M13/158 , H03M13/6575
摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

92. 发明申请

US20130007573A1 EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC 有权
标题翻译：有效和可扩展的循环冗余使用GALOIS-FIELD ARTIMETIC检查电路
公开(公告)号：US20130007573A1
公开(公告)日：2013-01-03
申请号：US13175500
申请日：2011-07-01
申请人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
发明人： Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/10 , G06F11/1076 , H03M1/1052 , H03M7/42 , H03M13/09 , H03M13/091 , H03M13/158 , H03M13/6575
摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.
摘要翻译：本公开的实施例描述了使用伽罗瓦域算术的循环冗余校验电路的方法，装置和系统配置。

93. 发明申请

US20140101460A1 ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES) 审中-公开
标题翻译：实施高级加密标准（AES）的架构和指导
公开(公告)号：US20140101460A1
公开(公告)日：2014-04-10
申请号：US14100970
申请日：2013-12-09
申请人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
发明人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
IPC分类号： G06F21/60
CPC分类号： H04L9/0631 , G06F9/30007 , G06F21/602 , H04L9/14 , H04L2209/24
摘要： A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
摘要翻译：提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

94. 发明申请

US20080159526A1 Architecture and instruction set for implementing advanced encryption standard (AES) 有权
标题翻译：实现高级加密标准（AES）的体系结构和指令集
公开(公告)号：US20080159526A1
公开(公告)日：2008-07-03
申请号：US11648434
申请日：2006-12-28
申请人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
发明人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0631 , G06F9/30007 , G06F21/602 , H04L9/14 , H04L2209/24
摘要： A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
摘要翻译：提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

95. 发明授权

US08914641B2 Method for signing and verifying data using multiple hash algorithms and digests in PKCS 有权
标题翻译：使用PKCS中的多个散列算法和摘要对数据进行签名和验证的方法
公开(公告)号：US08914641B2
公开(公告)日：2014-12-16
申请号：US13712401
申请日：2012-12-12
申请人： Vinodh Gopal , Sean M. Gulley , James D. Guilford , Wajdi K. Feghali
发明人： Vinodh Gopal , Sean M. Gulley , James D. Guilford , Wajdi K. Feghali
IPC分类号： H04L9/32
CPC分类号： H04L9/3247
摘要： Methods, systems, and apparatuses are disclosed for signing and verifying data using multiple hash algorithms and digests in PKCS including, for example, retrieving, at the originating computing device, a message for signing at the originating computing device to yield a signature for the message; identifying multiple hashing algorithms to be supported by the signature; for each of the multiple hashing algorithms identified to be supported by the signature, hashing the message to yield multiple hashes of the message corresponding to the multiple hashing algorithms identified; constructing a single digest having therein each of the multiple hashes of the messages corresponding to the multiple hashing algorithms identified and further specifying the multiple hashing algorithms to be supported by the signature; applying a signing algorithm to the single digest using a private key of the originating computing device to yield the signature for the message; and distributing the message and the signature to receiving computing devices. Other related embodiments are disclosed.
摘要翻译：公开了用于使用PKCS中的多个散列算法和摘要来签名和验证数据的方法，系统和装置，包括例如在起始计算设备处检索用于在始发计算设备处签名的消息以产生该消息的签名 ; 识别签名支持的多个散列算法; 对于被标识为被签名支持的多个散列算法中的每一个，散列消息以产生与识别的多个散列算法相对应的消息的多个哈希; 构建其中具有与识别的多个散列算法相对应的消息的多个散列中的每一个的单个摘要，并进一步指定要由签名支持的多个散列算法; 使用始发计算设备的私钥将签名算法应用于单个摘要以产生该消息的签名; 并将消息和签名分发给接收计算设备。公开了其他相关实施例。

96. 发明授权

US07949130B2 Architecture and instruction set for implementing advanced encryption standard (AES) 有权
标题翻译：实现高级加密标准（AES）的体系结构和指令集
公开(公告)号：US07949130B2
公开(公告)日：2011-05-24
申请号：US11648434
申请日：2006-12-28
申请人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
发明人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
IPC分类号： H04L9/28 , G06F15/00 , G06F12/14
CPC分类号： H04L9/0631 , G06F9/30007 , G06F21/602 , H04L9/14 , H04L2209/24
摘要： A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
摘要翻译：提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

97. 发明申请

US20080148025A1 High performance raid-6 system architecture with pattern matching 有权
标题翻译：具有模式匹配的高性能raid-6系统架构
公开(公告)号：US20080148025A1
公开(公告)日：2008-06-19
申请号：US11642315
申请日：2006-12-19
申请人： Vinodh Gopal , Gilbert Wolrich , Kirk S. Yap , Wajdi K. Feghali , John Vranich , Robert P. Ottavi
发明人： Vinodh Gopal , Gilbert Wolrich , Kirk S. Yap , Wajdi K. Feghali , John Vranich , Robert P. Ottavi
IPC分类号： G06F7/44
CPC分类号： G06F11/1076 , G06F2211/1057
摘要： An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.
摘要翻译：加速单元从处理器卸载计算密集型任务。加速单元包括两个数据处理路径，每个数据处理路径均具有算术逻辑单元并且共享单个乘法器单元。每个数据处理路径可以在相同的数据上并行地执行可配置的操作。提供特殊的多路复用器路径和指令以允许通过加速单元在数据的单程中在条带上计算P和Q型综合征。

98. 发明授权

US07664915B2 High performance raid-6 system architecture with pattern matching 有权
标题翻译：具有模式匹配的高性能raid-6系统架构
公开(公告)号：US07664915B2
公开(公告)日：2010-02-16
申请号：US11642315
申请日：2006-12-19
申请人： Vinodh Gopal , Gilbert Wolrich , Kirk S. Yap , Wajdi K. Feghali , John Vranich , Robert P. Ottavi
发明人： Vinodh Gopal , Gilbert Wolrich , Kirk S. Yap , Wajdi K. Feghali , John Vranich , Robert P. Ottavi
IPC分类号： G06F12/00
CPC分类号： G06F11/1076 , G06F2211/1057
摘要： An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.
摘要翻译：加速单元从处理器卸载计算密集型任务。加速单元包括两个数据处理路径，每个数据处理路径均具有算术逻辑单元并且共享单个乘法器单元。每个数据处理路径可以在相同的数据上并行地执行可配置的操作。提供特殊的多路复用器路径和指令以允许通过加速单元在数据的单程中在条带上计算P和Q型综合征。

99. 发明申请

US20080240426A1 Flexible architecture and instruction for advanced encryption standard (AES) 有权
标题翻译：高级加密标准（AES）的灵活架构和指令
公开(公告)号：US20080240426A1
公开(公告)日：2008-10-02
申请号：US11729199
申请日：2007-03-28
申请人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Makaram Raghunandan , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
发明人： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Makaram Raghunandan , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
IPC分类号： H04L9/28 , H04L9/00
CPC分类号： H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
摘要： A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
摘要翻译：提供了一种用于通用处理器的灵活的指令集。指令集包括对aes加密或解密执行“一轮”通行的指令，还包括执行密钥生成的指令。立即可以用于指示128/192/256位键的密钥生成的循环数和密钥大小。灵活的aes指令集可以充分利用流水线功能，因为它不需要跟踪隐式寄存器。

100. 发明申请

US20150043729A1 INSTRUCTION AND LOGIC TO PROVIDE A SECURE CIPHER HASH ROUND FUNCTIONALITY 审中-公开
标题翻译：指导和逻辑提供安全的水龙头功能
公开(公告)号：US20150043729A1
公开(公告)日：2015-02-12
申请号：US13962933
申请日：2013-08-08
申请人： Vinodh Gopal , Wajdi K. Feghali
发明人： Vinodh Gopal , Wajdi K. Feghali
IPC分类号： H04L9/06
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , H04L9/0625
摘要： Instructions and logic provide secure cipher hashing algorithm round functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a secure cipher hashing algorithm, the first instruction specifying a source data, and one or more key operands. Processor execution units, are responsive to the decoded instruction, to perform one or more secure cipher hashing algorithm round iterations upon the source data, using the one or more key operands, and store a result of the instruction in a destination register. One embodiment of the instruction specifies a secure cipher hashing algorithm round iteration using a Feistel cipher algorithm such as DES or TDES. In one embodiment a result of the instruction may be used in generating a resource assignment from a request for load balancing requests across the set of processing resources.
摘要翻译：指令和逻辑提供安全密码散列算法的圆功能。一些实施例包括处理器，包括：解码级，用于解码用于安全密码散列算法的指令，指定源数据的第一指令以及一个或多个键操作数。处理器执行单元响应于解码的指令，使用一个或多个键操作数对源数据执行一次或多次安全密码散列算法循环迭代，并将该指令的结果存储在目的地寄存器中。该指令的一个实施例使用诸如DES或TDES之类的Feistel密码算法来指定安全密码散列算法的圆迭代。在一个实施例中，指令的结果可以用于从整个处理资源集合的负载平衡请求请求生成资源分配。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式