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91. 发明授权

US08823175B2 Reliable area joints for power semiconductors 有权
标题翻译：功率半导体的可靠区域接头
公开(公告)号：US08823175B2
公开(公告)日：2014-09-02
申请号：US13471898
申请日：2012-05-15
申请人： Reinhold Bayerer
发明人： Reinhold Bayerer
IPC分类号： H01L23/48
CPC分类号： H01L23/3735 , H01L23/49534 , H01L23/49811 , H01L23/49833 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/73 , H01L2224/16238 , H01L2224/24011 , H01L2224/24105 , H01L2224/24226 , H01L2224/32225 , H01L2224/32227 , H01L2224/37147 , H01L2224/40095 , H01L2224/40105 , H01L2224/40225 , H01L2224/40227 , H01L2224/45124 , H01L2224/48472 , H01L2224/73203 , H01L2224/73263 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2924/00011 , H01L2924/00014 , H01L2924/10253 , H01L2924/10272 , H01L2924/1033 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13064 , H01L2924/13091 , H01L2924/00 , H01L2924/00012 , H01L2924/01005 , H01L2924/01033
摘要： A power semiconductor module includes an electrically insulating substrate, copper metallization disposed on a first side of the substrate and patterned into a die attach region and a plurality of contact regions, and a semiconductor die attached to the die attach region. The die includes an active device region and one or more copper die metallization layers disposed above the active device region. The active device region is disposed closer to the copper metallization than the one or more copper die metallization layers. The copper die metallization layer spaced furthest from the active device region has a contact area extending over a majority of a side of the die facing away from the substrate. The module further includes a copper interconnect metallization connected to the contact area of the die via an aluminum-free area joint and to a first one of the contact regions of the copper metallization.
摘要翻译：功率半导体模块包括电绝缘基板，设置在基板的第一侧上并被图案化成芯片附着区域和多个接触区域的铜金属化物，以及附着到管芯附着区域的半导体管芯。芯片包括有源器件区域和设置在有源器件区域上方的一个或多个铜管芯金属化层。有源器件区域比一个或多个铜管金属化层更靠近铜金属化。离开有源器件区域最远的铜管金属化层具有在芯片的背离衬底的一侧的大部分上延伸的接触区域。该模块还包括通过无铝区域接头和铜金属化接触区域中的第一个连接到管芯的接触区域的铜互连金属化。

92. 发明授权

US08466548B2 Semiconductor device including excess solder 有权
标题翻译：半导体器件包括多余的焊料
公开(公告)号：US08466548B2
公开(公告)日：2013-06-18
申请号：US13118748
申请日：2011-05-31
申请人： Reinhold Bayerer , Niels Oeschler , Alexander Ciliox
发明人： Reinhold Bayerer , Niels Oeschler , Alexander Ciliox
IPC分类号： H01L23/15 , H01L23/06 , H01L23/52 , H01L23/495 , H01L21/50 , H01L21/48
CPC分类号： H01L24/05 , H01L23/15 , H01L23/24 , H01L23/49844 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/072 , H01L2224/04026 , H01L2224/04042 , H01L2224/05564 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/26175 , H01L2224/291 , H01L2224/29111 , H01L2224/29147 , H01L2224/32013 , H01L2224/32225 , H01L2224/40227 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4847 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48664 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/48747 , H01L2224/48755 , H01L2224/48764 , H01L2224/48824 , H01L2224/48839 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/48864 , H01L2224/73263 , H01L2224/73265 , H01L2224/83205 , H01L2224/83385 , H01L2224/83439 , H01L2224/83444 , H01L2224/83455 , H01L2224/83464 , H01L2224/83801 , H01L2224/8381 , H01L2224/8382 , H01L2224/84801 , H01L2224/85205 , H01L2224/85439 , H01L2224/85444 , H01L2224/85455 , H01L2224/85464 , H01L2924/00014 , H01L2924/01047 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/12043 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2224/48227 , H01L2924/00012 , H01L2924/0105 , H01L2924/01028 , H01L2924/00 , H01L2924/01012 , H01L2224/05552 , H01L2224/37099 , H01L2224/8384
摘要： A semiconductor device includes a substrate including a first metal layer, a first semiconductor chip having sidewalls, and a first solder layer contacting the first semiconductor chip and the first metal layer. The first metal layer includes a groove extending around sidewalls of the first semiconductor chip. The groove is at least partly filled with excess solder from the first solder layer.
摘要翻译：半导体器件包括：衬底，其包括第一金属层，具有侧壁的第一半导体芯片和与第一半导体芯片和第一金属层接触的第一焊料层。第一金属层包括围绕第一半导体芯片的侧壁延伸的凹槽。沟槽至少部分地填充有来自第一焊料层的多余的焊料。

93. 发明申请

US20120235663A1 SEMICONDUCTOR DEVICE INCLUDING A CIRCUIT TO COMPENSATE FOR PARASITIC INDUCTANCE 有权
标题翻译：包括电路补偿电路的半导体器件
公开(公告)号：US20120235663A1
公开(公告)日：2012-09-20
申请号：US13048501
申请日：2011-03-15
申请人： Reinhold Bayerer , Piotr Luniewski
发明人： Reinhold Bayerer , Piotr Luniewski
IPC分类号： G05F3/08 , H02J1/00
CPC分类号： H03K17/168 , H01L2924/0002 , H02M1/088 , H03K17/16 , H03K17/166 , H01L2924/00
摘要： A semiconductor device includes a first transistor, a second transistor coupled in parallel with the first transistor, and a first parasitic inductance between an emitter of the first transistor and an emitter of the second transistor. The semiconductor device includes a first circuit configured to provide a first gate driver signal to the first transistor based on a common driver signal and a second circuit configured to provide a second gate driver signal to the second transistor based on the common driver signal. The first circuit and the second circuit are configured to compensate for a voltage drop across the first parasitic inductance such that the first gate driver signal and the second gate driver signal are in phase with and at the same magnitude as the common driver signal.
摘要翻译：半导体器件包括第一晶体管，与第一晶体管并联耦合的第二晶体管，以及第一晶体管的发射极和第二晶体管的发射极之间的第一寄生电感。半导体器件包括第一电路，其被配置为基于公共驱动器信号向第一晶体管提供第一栅极驱动器信号，以及第二电路，其被配置为基于公共驱动器信号向第二晶体管提供第二栅极驱动器信号。第一电路和第二电路被配置为补偿跨越第一寄生电感的电压降，使得第一栅极驱动器信号和第二栅极驱动器信号与公共驱动器信号同相并具有相同的幅度。

94. 发明授权

US08222928B2 Circuit arrangement including voltage supply circuit 有权
标题翻译：电路布置包括电源电路
公开(公告)号：US08222928B2
公开(公告)日：2012-07-17
申请号：US12571088
申请日：2009-09-30
申请人： Reinhold Bayerer
发明人： Reinhold Bayerer
IPC分类号： H03B1/00
CPC分类号： H03K17/567 , H03K2017/0806 , H03K2217/0081
摘要： One embodiment of a circuit arrangement includes first and second input voltage terminals for applying an input voltage, and at least one first semiconductor switching element having a drive terminal and a load path, the load path being connected between the input voltage terminals. A drive circuit is configured to receive a supply voltage, and has a drive output connected to the drive terminal of the at least one semiconductor switching element. A free-running oscillator is configured to generate an oscillating output voltage. A voltage supply circuit is provided for receiving the oscillating output voltage or a voltage dependent on the oscillating output voltage, and for providing the supply voltage of the drive circuit.
摘要翻译：电路装置的一个实施例包括用于施加输入电压的第一和第二输入电压端子以及具有驱动端子和负载路径的至少一个第一半导体开关元件，负载路径连接在输入电压端子之间。驱动电路被配置为接收电源电压，并且具有连接到所述至少一个半导体开关元件的驱动端子的驱动输出。自由振荡器被配置为产生振荡输出电压。提供电压供应电路用于接收振荡输出电压或取决于振荡输出电压的电压，以及用于提供驱动电路的电源电压。

95. 发明授权

US08222741B2 Semiconductor module with current connection element 有权
标题翻译：具有电流连接元件的半导体模块
公开(公告)号：US08222741B2
公开(公告)日：2012-07-17
申请号：US11693379
申请日：2007-03-29
申请人： Reinhold Bayerer , Guido Strotmann , Dirk Froebus , Reinhold Spanke
发明人： Reinhold Bayerer , Guido Strotmann , Dirk Froebus , Reinhold Spanke
IPC分类号： H01L23/52
CPC分类号： H01L25/072 , H01L23/49811 , H01L24/48 , H01L2224/48091 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor module having a current connection element designed for a high current carrying capability is disclosed. In one embodiment, the current connection element includes a plurality of metal layers which rest directly on one another.
摘要翻译：公开了一种具有设计用于高电流承载能力的电流连接元件的半导体模块。在一个实施例中，当前连接元件包括彼此直接放置的多个金属层。

96. 发明授权

US08198721B2 Semiconductor module 有权
标题翻译：半导体模块
公开(公告)号：US08198721B2
公开(公告)日：2012-06-12
申请号：US11487005
申请日：2006-07-14
申请人： Reinhold Bayerer , Thomas Licht , Dirk Siepe
发明人： Reinhold Bayerer , Thomas Licht , Dirk Siepe
IPC分类号： H01L23/48
CPC分类号： H01L23/3735 , H01L24/48 , H01L2224/48463 , H01L2224/73265 , H01L2224/8592 , H01L2924/00014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor substrate and a method for producing it is disclosed. In one embodiment, a contact region and a corresponding contact material of the semiconductor substrate are formed, in regions or completely, with a protection against oxidation.
摘要翻译：公开了一种半导体基板及其制造方法。在一个实施例中，半导体衬底的接触区域和对应的接触材料在区域中形成，或完全地形成，以防止氧化。

97. 发明申请

US20120080799A1 Semiconductor Module Comprising an Insert and Method for Producing a Semiconductor Module Comprising an Insert 有权
标题翻译：包括插入件的半导体模块和用于生成包括插入件的半导体模块的方法
公开(公告)号：US20120080799A1
公开(公告)日：2012-04-05
申请号：US12894645
申请日：2010-09-30
申请人： Olaf Hohlfeld , Reinhold Bayerer
发明人： Olaf Hohlfeld , Reinhold Bayerer
IPC分类号： H01L23/34 , H01L21/60
CPC分类号： H01L23/3735 , H01L23/24 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/072 , H01L2224/291 , H01L2224/29139 , H01L2224/29339 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/4846 , H01L2224/48472 , H01L2224/73265 , H01L2224/8384 , H01L2224/8584 , H01L2924/00014 , H01L2924/01327 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/181 , H01L2924/014 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： A power semiconductor module is fabricated by providing a base with a metal surface and an insulating substrate comprising an insulation carrier having a bottom side provided with a bottom metallization layer. An insert exhibiting a wavy structure is provided. The insert is positioned between the insulation carrier and metal surface, after which the metal surface is soldered to the bottom side metallization layer and insert by means of a solder packing all interstices between the metal surface and bottom side metallization layer with the solder.
摘要翻译：通过提供具有金属表面的基底和包括具有设置有底部金属化层的底侧的绝缘载体的绝缘基底来制造功率半导体模块。提供具有波浪形结构的插入件。插入件位于绝缘载体和金属表面之间，然后将金属表面焊接到底侧金属化层，并通过焊料填充金属表面和底侧金属化层之间的所有间隙与焊料插入。

98. 发明申请

US20110070695A1 METHOD OF FABRICATING A HIGH-TEMPERATURE COMPATIBLE POWER SEMICONDUCTOR MODULE 有权
标题翻译：制造高温兼容功率半导体模块的方法
公开(公告)号：US20110070695A1
公开(公告)日：2011-03-24
申请号：US12883406
申请日：2010-09-16
申请人： Reinhold Bayerer
发明人： Reinhold Bayerer
IPC分类号： H01L21/50
CPC分类号： H01L24/85 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/83 , H01L25/072 , H01L2224/29111 , H01L2224/32225 , H01L2224/32507 , H01L2224/45014 , H01L2224/45015 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/4903 , H01L2224/49051 , H01L2224/73265 , H01L2224/78313 , H01L2224/83192 , H01L2224/83801 , H01L2224/8381 , H01L2224/83825 , H01L2224/8384 , H01L2224/85186 , H01L2224/92 , H01L2224/92247 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01327 , H01L2924/0133 , H01L2924/014 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/15787 , H01L2924/2076 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： The invention relates to a method for fabricating a high-temperature compatible power semiconductor module in which a power semiconductor chip is bonded by means of a diffusion solder layer to a substrate and said substrate is bonded by means of silver sintered layer to a base plate, after which a bonding element is bonded to the top chip metallization. To prevent oxidation of the predefined bond area when producing the diffusion solder layer and the sintered silver layer 4′ an anti-oxidation layer is applied to the top chip metallization at least in the region of the predefined bond area.
摘要翻译：本发明涉及一种用于制造高温兼容功率半导体模块的方法，其中功率半导体芯片通过扩散焊料层与衬底接合，所述衬底通过银烧结层与基板接合，之后，结合元件被结合到顶部芯片金属化。为了防止在制造扩散焊料层和烧结银层4'时预定的粘合区域的氧化，至少在预定粘结区域的区域中，将抗氧化层施加到顶部金属化。

99. 发明授权

US07910952B2 Power semiconductor arrangement 有权
标题翻译：功率半导体布置
公开(公告)号：US07910952B2
公开(公告)日：2011-03-22
申请号：US11863463
申请日：2007-09-28
申请人： Roman Tschirbs , Reinhold Bayerer
发明人： Roman Tschirbs , Reinhold Bayerer
IPC分类号： H01L23/48
CPC分类号： H01L23/3735 , H01L23/4006 , H01L23/492 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/072 , H01L2023/4031 , H01L2023/4056 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4846 , H01L2224/48472 , H01L2224/49 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45099
摘要： One aspect relates to a power semiconductor arrangement includes a power semiconductor module which is mechanically connected to a heat sink. In order to improve the thermal cycling stability of the connection between a baseplate of the module and a circuit carrier connected thereto, recesses are provided in the baseplate. One aspect further relates to a power semiconductor module.
摘要翻译：一个方面涉及功率半导体装置，其包括机械地连接到散热器的功率半导体模块。为了提高模块的基板与与其连接的电路载体之间的连接的热循环稳定性，在基板中设置凹部。一个方面还涉及功率半导体模块。

100. 发明申请

US20110053319A1 Method for Fabricating a Circuit Substrate Assembly and a Power Electronics Module Comprising an Anchoring Structure for Producing a Changing Temperature-Stable Solder Bond 有权
标题翻译：用于制造电路基板组件的方法和包括用于产生改变的温度稳定焊接键的锚定结构的电力电子模块
公开(公告)号：US20110053319A1
公开(公告)日：2011-03-03
申请号：US12850374
申请日：2010-08-04
申请人： Olaf Hohlfeld , Jens Goerlich , Reinhold Bayerer
发明人： Olaf Hohlfeld , Jens Goerlich , Reinhold Bayerer
IPC分类号： H01L21/58
CPC分类号： H01L23/3735 , H01L23/24 , H01L23/49811 , H01L24/28 , H01L24/29 , H01L24/39 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/072 , H01L2224/29339 , H01L2224/32225 , H01L2224/45015 , H01L2224/48091 , H01L2224/4846 , H01L2224/48472 , H01L2224/49 , H01L2224/73265 , H01L2224/83801 , H01L2224/8384 , H01L2224/8385 , H01L2224/8584 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01028 , H01L2924/01046 , H01L2924/01068 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/0781 , H01L2924/12043 , H01L2924/1301 , H01L2924/13034 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/181 , H01L2924/2076 , H05K1/0203 , H05K1/0306 , H05K3/0061 , H05K3/341 , H05K2201/0373 , H01L2924/3512 , H01L2924/00 , H01L2224/48227 , H01L2924/00012 , H01L2224/45099 , H01L2224/37099
摘要： A power semiconductor module is fabricated by providing a circuit substrate with a metal surface and an insulating substrate comprising an insulation carrier featuring a bottom side provided with a bottom metallization layer. An anchoring structure is provided comprising a plurality of oblong pillars each featuring a first end facing away from the insulation carrier, at least a subset of the pillars being distributed over the anchoring structure in its entirety, it applying for each of the pillars of the subset that from a sidewall thereof no or a maximum of three elongated bonding webs each extend to a sidewall of another pillar where they are bonded thereto. The anchoring structure is positioned between the insulation carrier and metal surface, after which the metal surface is soldered to the bottom metallization layer and anchoring structure by means of a solder packing all interstices between the metal surface and bottom metallization layer with the solder.
摘要翻译：通过为电路基板提供金属表面和绝缘基板来制造功率半导体模块，所述绝缘基板包括具有设置有底部金属化层的底侧的绝缘载体。提供了一种锚固结构，其包括多个长方形支柱，每个长方形支柱具有背离绝缘载体的第一端，所述支柱的至少一部分整体分布在锚固结构上，它应用于子集的每个柱从其侧壁没有或最多三个细长的粘合幅材每个延伸到另一个柱的侧壁，在其另一个柱的侧壁上。锚固结构位于绝缘载体和金属表面之间，之后通过焊料将金属表面焊接到底部金属化层和锚定结构，所述金属表面与金属表面和底部金属化层之间的所有间隙都与焊料焊接。

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