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91. 发明授权

US07110006B2 Video, audio and graphics decode, composite and display system 有权
公开(公告)号：US07110006B2
公开(公告)日：2006-09-19
申请号：US10997652
申请日：2004-11-23
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Greg A. Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
IPC分类号： H04N5/445 , G09G5/00 , G06F13/00 , H04N5/45 , G09G7/01 , G09G11/20
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

92. 发明授权

US07092831B2 System and method for determining signal consistency 失效
标题翻译：用于确定信号一致性的系统和方法
公开(公告)号：US07092831B2
公开(公告)日：2006-08-15
申请号：US10884905
申请日：2004-07-06
申请人： Alexander G. MacInnis
发明人： Alexander G. MacInnis
IPC分类号： G06F19/00
CPC分类号： H04N9/44 , H04N5/073
摘要： A system and method for determining signal consistency (e.g., in a video signal processing system) are disclosed. Various aspects of the present invention may, for example, include receiving a first and second signal, each of which includes respective first and second sub-signals. A receiving module may, for example, effect such receiving. The first and second signals may be synchronized according to, at least in part, aspects of their respective first sub-signals. A signal synchronization module may, for example, effect such synchronization. Relative timing between the respective second sub-signals of the first and second synchronized signals may be determined. A timing differential module may, for example, effect such a determination. Various aspects of the present invention may generate a signal indicative of signal consistency based, at least in part, on the determination of relative timing between the respective second sub-signals. An output module may, for example, effect such a signal generation.
摘要翻译：公开了一种用于确定信号一致性的系统和方法（例如，在视频信号处理系统中）。本发明的各个方面可以例如包括接收第一和第二信号，每个信号包括相应的第一和第二子信号。接收模块例如可以实现这种接收。第一和第二信号可以至少部分地根据它们各自的第一子信号的方面进行同步。信号同步模块例如可以实现这种同步。可以确定第一和第二同步信号的各个第二子信号之间的相对定时。定时差分模块可以例如实现这样的确定。本发明的各个方面可以至少部分地基于确定相应的第二子信号之间的相对定时来产生指示信号一致性的信号。例如，输出模块可以产生这样的信号。

93. 发明授权

US07057622B2 Graphics display system with line buffer control scheme 失效
公开(公告)号：US07057622B2
公开(公告)日：2006-06-06
申请号：US10423364
申请日：2003-04-25
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G5/36 , G09G5/00
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.

94. 发明授权

US06879330B2 Graphics display system with anti-flutter filtering and vertical scaling feature 有权
标题翻译：图形显示系统具有防颤滤波和垂直缩放功能
公开(公告)号：US06879330B2
公开(公告)日：2005-04-12
申请号：US10842743
申请日：2004-05-10
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06T9/00 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/395 , G09G5/42 , H04N5/12 , H04N5/14 , H04N5/44 , H04N5/445 , H04N5/45 , H04N5/46 , H04N7/01 , H04N7/26 , H04N7/50 , H04N9/45 , H04N9/64 , H04N11/14 , H04N11/20 , H04N21/422 , H04N21/426 , H04N21/43 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/47 , H04N7/701
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形集成电路芯片。图形芯片处理模拟视频输入，数字视频输入和图形输入。该芯片包括单个多相滤波器，其优选地提供图像的防颤音滤波和缩放。防颤音滤波可能有助于减少由于电视显示器的隔行特性引起的显示闪烁。图形的缩放可以用于将图形的正方形像素长宽比转换为视频的正常矩形像素长宽比。

95. 发明授权

US06768774B1 Video and graphics system with video scaling 有权
标题翻译：具有视频缩放功能的视频和图形系统
公开(公告)号：US06768774B1
公开(公告)日：2004-07-27
申请号：US09640870
申请日：2000-08-18
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Vivian Hsiun
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Vivian Hsiun
IPC分类号： H04N7112
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/143 , H04N11/20 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4307 , H04N21/4316 , H04N21/4347 , H04N21/440218 , H04N21/44029
摘要： A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.
摘要翻译：视频和图形系统具有减小的存储模式，其中视频图像在解码期间在水平方向上减少一半。视频和图形系统包括用于解码MPEG-2视频数据的视频解码器。当不使用双向预测图像时，视频图像可能在水平方向上可能不被缩小。视频和图形系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。具有SDTV格式的输出可以在显示HDTV视频时使用录像机（VCR）进行记录。

96. 发明授权

US06630945B1 Graphics display system with graphics window control mechanism 有权
公开(公告)号：US06630945B1
公开(公告)日：2003-10-07
申请号：US09437581
申请日：1999-11-09
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G500
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip processes graphics images organized as windows. The chip obtains data that describes the windows, sorts the data according to the depth of the window on the display, transfers graphics images from memory, and blends the graphics images using alpha values associated with the graphics images.

97. 发明授权

US06570579B1 Graphics display system 有权
标题翻译：图形显示系统
公开(公告)号：US06570579B1
公开(公告)日：2003-05-27
申请号：US09437208
申请日：1999-11-09
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie
IPC分类号： G09G500
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip incorporates a unified memory architecture that provides a high level of system performance while conserving memory bandwidth and chip size. Video and graphics scaling capabilities as well as anti-flutter filtering capability are provided.
摘要翻译：在机顶盒中使用图形集成电路来控制电视显示器。图形芯片同时处理模拟视频输入，数字视频输入，图形输入和音频输入。该芯片结合了统一的内存架构，提供高水平的系统性能，同时节省内存带宽和芯片大小。提供了视频和图形缩放功能以及防颤音滤波功能。

98. 发明授权

US10334288B2 Method and system for zero overhead parallel entropy decoding 有权
公开(公告)号：US10334288B2
公开(公告)日：2019-06-25
申请号：US13158061
申请日：2011-06-10
申请人： Alexander G. MacInnis
发明人： Alexander G. MacInnis
IPC分类号： H04N19/44 , H04N21/24 , H04N21/44 , H04N19/436 , H04N21/236 , H04N21/434 , H04N21/2343
摘要： Certain embodiments of the invention may be found in a system and/or method for zero overhead parallel entropy decoding. Exemplary aspects of the invention may comprise a decoder that comprises a demultiplexer. An encoded bit stream may be demultiplexed into a plurality of sub-streams. The encoded bit stream may be constructed without adding one or more bits to the encoded bit stream to facilitate the demultiplexing. Exemplary aspects of the invention may also comprise an encoder that comprises a multiplexer. Each of a plurality of encoded sub-streams may be multiplexed into an encoded bit stream. The encoded bit stream may be constructed without adding one or more bits to the encoded bit stream to indicate the multiplexing.

99. 发明授权

US09774875B2 Lossless and near-lossless image compression 有权
公开(公告)号：US09774875B2
公开(公告)日：2017-09-26
申请号：US12720273
申请日：2010-03-09
申请人： Alexander G. MacInnis , Lei Zhang
发明人： Alexander G. MacInnis , Lei Zhang
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04N19/426 , H04N19/61 , H04N19/124 , H04N19/423
CPC分类号： H04N19/426 , H04N19/124 , H04N19/423 , H04N19/61
摘要： Presented herein is lossless and near-lossless image compression. In one embodiment, there is described a method for encoding data. The method comprises receiving said data; quantizing a predetermined amount of the data with a predetermined quantization step; determining how many bits represent the predetermined amount of the data quantized with the predetermined quantization step; and wherein if the amount of data exceeds a predetermined amount of bits, changing the quantization step.

100. 发明授权

US09417883B2 Video decoding system supporting multiple standards 有权
公开(公告)号：US09417883B2
公开(公告)日：2016-08-16
申请号：US13608221
申请日：2012-09-10
申请人： Alexander G. MacInnis , Jose′ R. I. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
发明人： Alexander G. MacInnis , Jose′ R. I. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
IPC分类号： H04N19/423 , G06F9/38 , H04N19/176 , H04N19/70 , H04N19/122 , H04N19/129 , H04N19/61 , H04N19/60 , H04N19/12 , H04N19/91 , H04N19/157 , H04N19/44 , H04N19/82 , H04N19/90 , H04N19/625
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
摘要： System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

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