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91. 发明授权

US08902629B2 Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device 有权
标题翻译：在可变电阻非易失性存储元件上形成的形成方法以及可变电阻非易失性存储器件
公开(公告)号：US08902629B2
公开(公告)日：2014-12-02
申请号：US13511275
申请日：2011-09-28
申请人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama , Shunsaku Muraoka
发明人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama , Shunsaku Muraoka
IPC分类号： G11C11/00 , H01L45/00 , H01L27/10 , H01L27/24 , G11C13/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier (303) for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FF1 to FFn and a clock signal CLK. Thereby, a switch transistor (301) is in a non-conducting state and the forming on a variable resistance element is automatically terminated.
摘要翻译：在形成时，包括在非易失性存储器件（200）中的自动形成电路（210）使得恒定电流IL流过具有相当高的初始电阻的所选择的存储单元。当形成在存储单元中产生细丝通路并由此电阻值减小时，节点NBL的电位和节点Nin的电位也减小。如果电位变得低于参考电压Vref的电位，则激活用于检测成形成功的差分放大器（303）的输出NO，并且根据触发器的数量n在延迟时间之后激活形成成功信号Vfp FF1〜FFn和时钟信号CLK。由此，开关晶体管（301）处于非导通状态，可变电阻元件上的形成自动终止。

92. 发明授权

US08848421B2 Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device 有权
标题翻译：在可变电阻非易失性存储元件上形成的形成方法以及可变电阻非易失性存储器件
公开(公告)号：US08848421B2
公开(公告)日：2014-09-30
申请号：US13634161
申请日：2011-03-28
申请人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama
发明人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama
IPC分类号： G11C11/00 , H01L45/00 , H01L27/10 , G11C13/00 , H01L27/24
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A forming method of a variable resistance nonvolatile memory element capable of lowering a forming voltage and preventing variations of the forming voltage depending on variable resistance elements. The forming method is for initializing a variable resistance element, including a step (S24) of determining whether or not a current flowing in a 1T1R memory cell is greater than a reference current; a step (S22) of applying a forming positive voltage pulse having a pulse width (Tp(n)) is gradually increased when it is determined that the current is not greater than the reference current; and a step (S23) of applying a negative voltage pulse having a pulse width Tn equal to or shorter than a pulse width Tp(n). The determining step (S24), the application step (S22), and the application step (S23) are repeated until the forming becomes successful.
摘要翻译：一种可变电阻非易失性存储元件的形成方法，其能够降低形成电压并防止取决于可变电阻元件的形成电压的变化。该形成方法用于初始化可变电阻元件，包括确定在1T1R存储单元中流动的电流是否大于参考电流的步骤（S24）; 当确定电流不大于参考电流时，施加具有脉冲宽度（Tp（n））的形成正电压脉冲的步骤（S22）逐渐增加; 以及施加脉冲宽度Tn等于或短于脉冲宽度Tp（n）的负电压脉冲的步骤（S23）。重复确定步骤（S24），应用步骤（S22）和应用步骤（S23），直到形成成功。

93. 发明授权

US08565004B2 Nonvolatile memory device and method for programming the same 有权
标题翻译：非易失性存储器件及其编程方法
公开(公告)号：US08565004B2
公开(公告)日：2013-10-22
申请号：US13379463
申请日：2011-06-28
申请人： Mitsuteru Iijima , Takeshi Takagi , Koji Katayama
发明人： Mitsuteru Iijima , Takeshi Takagi , Koji Katayama
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A method for programming a nonvolatile memory device according to the present invention includes a step of detecting an excessively low resistance cell from among a plurality of memory cells (11) (S101); a step of changing the resistance value of a load resistor (121) to a second resistance value smaller than a first resistance value (S103); and a step of causing, by applying a voltage pulse to a series circuit including the excessively low resistance cell and the load resistor (121) having the second resistance value, a variable resistance element (105) included in the excessively low resistance cell to shift to a second high resistance state having a resistance value greater than that of the first low resistance state (S104).
摘要翻译：根据本发明的非易失性存储器件的编程方法包括从多个存储单元（11）中检测过低电阻单元的步骤（S101）; 将负载电阻器（121）的电阻值改变为小于第一电阻值的第二电阻值的步骤（S103）; 以及通过对包括过低电阻单元的串联电路和具有第二电阻值的负载电阻器（121）施加电压脉冲，使包含在过低电阻单元中的可变电阻元件（105）移位到具有大于第一低电阻状态的电阻值的第二高电阻状态（S104）。

94. 发明授权

US08553446B2 Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor device incorporating nonvolatile memory element 有权
标题翻译：非易失性存储元件，其制造方法和非易失性存储元件的非易失性半导体器件
公开(公告)号：US08553446B2
公开(公告)日：2013-10-08
申请号：US13567646
申请日：2012-08-06
申请人： Satoru Mitani , Yoshihiko Kanzawa , Koji Katayama , Takeshi Takagi
发明人： Satoru Mitani , Yoshihiko Kanzawa , Koji Katayama , Takeshi Takagi
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/79 , H01L27/101 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9≦x≦1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8
摘要翻译：本发明的非易失性存储元件包括第一电极（103），第二电极（108）介于第一电极（103）和第二电极（107）之间的电阻变化层（107），其被配置为响应于施加在电极（103）和（108）之间的电信号可逆地切换电阻值，，并且电阻变化层（107）具有至少多层结构，其中具有表示为HfO x（0.9 @ x @ 1.6）的组成的第一含铪层和具有表达的组成的第二含铪层因为HfOy（1.8

95. 发明申请

US20130223131A1 METHOD FOR DRIVING VARIABLE RESISTANCE ELEMENT, AND NONVOLATILE MEMORY DEVICE 有权
标题翻译：驱动可变电阻元件的方法和非易失性存储器件
公开(公告)号：US20130223131A1
公开(公告)日：2013-08-29
申请号：US13883075
申请日：2012-06-11
申请人： Takeshi Takagi , Koji Katayama
发明人： Takeshi Takagi , Koji Katayama
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/32
摘要： A driving method for driving a variable resistance element and a nonvolatile memory device, which achieves stable storage operation. In a low resistance write process, a low resistance writing voltage pulse having the negative polarity is applied once to a variable resistance layer included in a variable resistance element while in a high resistance write process, a high resistance writing voltage pulse having the positive polarity is applied more than twice to the same variable resistance layer. Here, when a voltage value of one of the high resistance writing voltage pulses is VH1 and a voltage value of the other high resistance writing voltage pulse applied subsequently is VH2, VH1>VH2 is satisfied.
摘要翻译：用于驱动可变电阻元件和非易失性存储器件的驱动方法，其实现稳定的存储操作。在低电阻写入处理中，具有负极性的低电阻写入电压脉冲在包括在可变电阻元件中的可变电阻层上施加一次，而在高电阻写入处理中，具有正极性的高电阻写入电压脉冲是施加两倍以上的同一可变电阻层。这里，当高电阻写入电压脉冲之一的电压值为VH1，随后施加的另一个高电阻写入电压脉冲的电压值为VH2时，满足VH1> VH2。

96. 发明申请

US20130044534A1 FORMING METHOD OF PERFORMING FORMING ON VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：形成可变电阻非易失性存储器元件和可变电阻非易失性存储器件的形成方法
公开(公告)号：US20130044534A1
公开(公告)日：2013-02-21
申请号：US13634161
申请日：2011-03-28
申请人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama
发明人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A forming method of a variable resistance nonvolatile memory element capable of lowering a forming voltage and preventing variations of the forming voltage depending on variable resistance elements. The forming method is for initializing a variable resistance element, including a step (S24) of determining whether or not a current flowing in a 1T1R memory cell is greater than a reference current; a step (S22) of applying a forming positive voltage pulse having a pulse width (Tp(n)) is gradually increased when it is determined that the current is not greater than the reference current; and a step (S23) of applying a negative voltage pulse having a pulse width Tn equal to or shorter than a pulse width Tp(n). The determining step (S24), the application step (S22), and the application step (S23) are repeated until the forming becomes successful.
摘要翻译：一种可变电阻非易失性存储元件的形成方法，其能够降低形成电压并防止取决于可变电阻元件的形成电压的变化。该形成方法用于初始化可变电阻元件，包括确定在1T1R存储单元中流动的电流是否大于参考电流的步骤（S24）; 当确定电流不大于参考电流时，施加具有脉冲宽度（Tp（n））的形成正电压脉冲的步骤（S22）逐渐增加; 以及施加脉冲宽度Tn等于或短于脉冲宽度Tp（n）的负电压脉冲的步骤（S23）。重复确定步骤（S24），应用步骤（S22）和应用步骤（S23），直到形成成功。

97. 发明申请

US20130010530A1 METHOD FOR DRIVING NON-VOLATILE MEMORY ELEMENT, AND NON-VOLATILE MEMORY DEVICE 有权
标题翻译：驱动非易失性存储器元件的方法和非易失性存储器件
公开(公告)号：US20130010530A1
公开(公告)日：2013-01-10
申请号：US13636258
申请日：2011-03-18
申请人： Koji Katayama , Takeshi Takagi , Mitsuteru Iijima
发明人： Koji Katayama , Takeshi Takagi , Mitsuteru Iijima
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/72 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： Provided is a method for driving a non-volatile memory element in which a variable resistance element including a first electrode, a second electrode, and a variable resistance layer capable of reversibly changing between a high resistance state and a low resistance state with application of electrical signals having different polarities is connected in series with a current steering element having bidirectional rectifying characteristics with respect to an applied voltage. After the non-volatile memory element is manufactured, the resistance value of the variable resistance layer is reduced from a resistance value in the initial resistance state higher than that in the high resistance state by applying, to the non-volatile memory element, a voltage pulse having the polarity identical to that of the voltage pulse for changing the variable resistance layer from the low resistance state to the high resistance state in the normal operations.
摘要翻译：提供一种用于驱动非易失性存储元件的方法，其中包括第一电极，第二电极和可变电阻层的可变电阻元件，所述可变电阻元件能够通过施加电而在高电阻状态和低电阻状态之间可逆地变化具有不同极性的信号与具有相对于施加电压的双向整流特性的电流导向元件串联连接。在制造非易失性存储元件之后，通过向非易失性存储元件施加电压，可变电阻层的电阻值比初始电阻状态中的电阻值高于高电阻状态的电阻值脉冲具有与用于在正常操作中将可变电阻层从低电阻状态改变为高电阻状态的电压脉冲的极性相同的脉冲。

98. 发明申请

US20120320661A1 METHOD OF PROGRAMMING VARIABLE RESISTANCE ELEMENT AND NONVOLATILE STORAGE DEVICE 有权
标题翻译：可变电阻元件和非易失性存储器件的编程方法
公开(公告)号：US20120320661A1
公开(公告)日：2012-12-20
申请号：US13596154
申请日：2012-08-28
申请人： Shunsaku MURAOKA , Takeshi Takagi , Satoru Mitani , Koji Katayama
发明人： Shunsaku MURAOKA , Takeshi Takagi , Satoru Mitani , Koji Katayama
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0083 , G11C2213/72 , G11C2213/79 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A method includes applying a first polarity writing voltage pulse to a metal oxide layer to change its resistance state from high to low into a write state, applying a second polarity erasing voltage pulse different from the first polarity to the metal oxide layer to change its resistance state from low to high into an erase state, and applying an initial voltage pulse having the second polarity to the metal oxide layer before first application of the writing voltage pulse, to change an initial resistance value of the metal oxide layer. R0>RH>RL and |V0|>|Ve|≧|Vw| are satisfied where R0, RL, and RH are the resistance values of the initial, write, and erase states, respectively, of the metal oxide layer, and V0, Vw, and Ve are voltage values of the initial, writing, and erasing voltage pulses, respectively.
摘要翻译：一种方法包括：将第一极性写入电压脉冲施加到金属氧化物层，以将其电阻状态从高变为低电平变为写入状态，将不同于第一极性的第二极性擦除电压脉冲施加到金属氧化物层以改变其电阻状态从低到高进入擦除状态，以及在首次施加写入电压脉冲之前将具有第二极性的初始电压脉冲施加到金属氧化物层，以改变金属氧化物层的初始电阻值。 R0> RH> RL和| V0 |> | Ve |≥| Vw | 满足R0，RL和RH分别是金属氧化物层的初始，写入和擦除状态的电阻值，V0，Vw和Ve是初始，写入和擦除电压的电压值脉冲。

99. 发明授权

US08264865B2 Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor device incorporating nonvolatile memory element 有权
标题翻译：非易失性存储元件，其制造方法和非易失性存储元件的非易失性半导体器件
公开(公告)号：US08264865B2
公开(公告)日：2012-09-11
申请号：US12677404
申请日：2009-07-01
申请人： Satoru Mitani , Yoshihiko Kanzawa , Koji Katayama , Takeshi Takagi
发明人： Satoru Mitani , Yoshihiko Kanzawa , Koji Katayama , Takeshi Takagi
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/79 , H01L27/101 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9≦x≦1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8
摘要翻译：本发明的非易失性存储元件包括第一电极（103），第二电极（108）介于第一电极（103）和第二电极（107）之间的电阻变化层（107），其被配置为响应于施加在电极（103）和（108）之间的电信号可逆地切换电阻值，，并且电阻变化层（107）具有至少多层结构，其中具有表示为HfO x（0.9＆nlE; x＆nlE; 1.6）的组成的第一含铪层和具有组成的第二含铪层表示为HfOy（1.8

100. 发明授权

US08227279B2 Manufacturing method of a semiconductor element 失效
标题翻译：半导体元件的制造方法
公开(公告)号：US08227279B2
公开(公告)日：2012-07-24
申请号：US12539355
申请日：2009-08-11
申请人： Koji Katayama , Hiroyuki Kitabayashi , Satoshi Arakawa
发明人： Koji Katayama , Hiroyuki Kitabayashi , Satoshi Arakawa
IPC分类号： H01L21/00
CPC分类号： H01L21/3081 , H01L21/32139
摘要： A method of manufacturing a semiconductor element of good characteristics at a reduced manufacturing cost is provided. The manufacturing method of the semiconductor element includes a GaN-containing semiconductor layer forming step, an electrode layer forming step, a step of forming an Al film on the GaN-containing semiconductor layer, a step of forming a mask layer made of a material of which etching rate is smaller than that of a material of the Al film, a step of forming a ridge portion using the mask layer as a mask, a step of retreating a position of a side wall of the Al film with respect to a position of a side wall of the mask layer, a step of forming, on the side surface of the ridge portion and the top surface of the mask layer, a protective film made of a material of which etching rate is smaller than that of the material forming the Al film, and a step of removing the Al film and thereby removing the mask layer and a portion of the protective film formed on the top surface of the mask layer.
摘要翻译：提供一种以降低的制造成本制造具有良好特性的半导体元件的方法。半导体元件的制造方法包括含GaN半导体层形成工序，电极层形成工序，在含GaN半导体层上形成Al膜的工序，形成掩模层的工序，该蚀刻速率小于Al膜的材料的蚀刻速率，使用该掩模层作为掩模形成脊部的步骤，相对于Al膜的位置退回Al膜的侧壁的位置的步骤掩模层的侧壁，在脊部的侧表面和掩模层的顶表面上形成保护膜，该保护膜的蚀刻速率小于形成该掩模层的材料的蚀刻速率的材料 Al膜，以及除去Al膜，从而除去掩模层和形成在掩模层的顶表面上的保护膜的一部分的步骤。

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