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91. 发明申请

US20080079064A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080079064A1
公开(公告)日：2008-04-03
申请号：US11898528
申请日：2007-09-13
申请人： Sheng-Chih Lai , Hang-Ting Lue
发明人： Sheng-Chih Lai , Hang-Ting Lue
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/517 , H01L29/513 , H01L29/66833 , H01L29/792
摘要： A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.
摘要翻译：提供了具有非易失性存储器的半导体器件及其制造方法。半导体器件包括基底材料和堆叠结构。设置在基材上的堆叠结构至少包括隧穿层，捕获层和电介质层。捕获层设置在隧道层上。电介质层具有介电常数并且设置在捕获层上。当电介质层进行处理时，电介质层从第一固态转变为第二固态。

92. 发明申请

US20080002477A1 METHOD FOR MANUFACTURING MEMORY CELL 有权
标题翻译：制造记忆细胞的方法
公开(公告)号：US20080002477A1
公开(公告)日：2008-01-03
申请号：US11836142
申请日：2007-08-09
申请人： Tzu-Hsuan Hsu , Erh-Kun Lai , Hang-Ting Lue , Chia-Hua Ho
发明人： Tzu-Hsuan Hsu , Erh-Kun Lai , Hang-Ting Lue , Chia-Hua Ho
IPC分类号： G11C11/34 , H01L21/36
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/42352
摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.
摘要翻译：本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构底物。存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。跨门位于基板上，跨越垂直翅片结构。载体捕获层位于跨门和基板之间。源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

93. 发明授权

US07315474B2 Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays 有权
标题翻译：非易失性存储器单元，包括相同的存储器阵列以及操作单元和阵列的方法
公开(公告)号：US07315474B2
公开(公告)日：2008-01-01
申请号：US11324581
申请日：2006-01-03
申请人： Hang-Ting Lue
发明人： Hang-Ting Lue
IPC分类号： G11C11/34
CPC分类号： H01L29/792 , G11C16/0483 , G11C16/0491 , H01L21/265 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.
摘要翻译：存储单元包括：半导体衬底，其具有设置在衬底的表面下方并由沟道区分隔开的源极区和漏极区; 隧道电介质结构，其设置在所述沟道区上方，所述隧道介电结构包括至少一层具有小的空穴隧道势垒高度的层; 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且描述设置在绝缘层上方的栅极电极及其阵列和操作方法。

94. 发明申请

US20070258289A1 Method of Programming and Erasing a P-Channel BE-SONOS NAND Flash Memory 有权
标题翻译：编程和擦除P通道BE-SONOS NAND闪存的方法
公开(公告)号：US20070258289A1
公开(公告)日：2007-11-08
申请号：US11381760
申请日：2006-05-05
申请人： Hang-Ting Lue
发明人： Hang-Ting Lue
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/12 , G11C16/3418 , G11C16/3427
摘要： A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.
摘要翻译：一种用于p沟道存储单元的编程方法，所述存储单元包括源极，漏极和栅极。门施加第一电压，这导致Fowler-Nordheim（-FN）空穴注入，从而使存储器单元处于编程状态。

95. 发明申请

US20060205157A1 Non-volatile memory and method for fabricating the same 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20060205157A1
公开(公告)日：2006-09-14
申请号：US11429070
申请日：2006-05-05
申请人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
发明人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42348 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.
摘要翻译：提供非易失性存储器。存储器包括衬底，电介质层，导电层，隔离层，掩埋位线，隧道电介质层，电荷俘获层，势垒介电层和字线。其中介电层设置在基板上。导电层设置在电介质层上。隔离层设置在基板上并且邻近电介质层和导电层。掩埋位线设置在衬底中并在隔离层下方。隧道电介质层设置在导电层和隔离层的基板和侧壁上。电荷捕获层设置在隧道介电层上，势垒介电层设置在电荷俘获层上。字线设置在基板上，与埋入位线交叉。

96. 发明授权

US07067375B1 Non-volatile memory and method for fabricating the same 有权
公开(公告)号：US07067375B1
公开(公告)日：2006-06-27
申请号：US11018507
申请日：2004-12-20
申请人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
发明人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42348 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

97. 发明授权

US08861273B2 Bandgap engineered charge trapping memory in two-transistor nor architecture 有权
标题翻译：带隙设计的电荷俘获存储器在双晶体管和架构中
公开(公告)号：US08861273B2
公开(公告)日：2014-10-14
申请号：US12427587
申请日：2009-04-21
申请人： Hang-Ting Lue
发明人： Hang-Ting Lue
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L27/115 , H01L29/51
CPC分类号： H01L21/28282 , G11C16/0433 , H01L27/11565 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要： A 2T cell NOR architecture based on the use of BE-SONOS for embedded memory includes memory cells having respective access transistors having access gates and memory transistors having memory gates arranged in series between the corresponding bit lines and one of the plural reference lines. A memory transistor in a memory cell comprises a semiconductor body including a channel having a channel surface and a charge storing dielectric stack between the memory gate and the channel surface. The dielectric stack comprises a bandgap engineered, tunneling dielectric layer contacting one of the gate (for gate injection tunneling) and the channel surface (for channel injection tunneling). The dielectric stack of the memory cell also includes a charge trapping dielectric layer on the tunneling dielectric layer and a blocking dielectric layer.
摘要翻译：基于对嵌入式存储器使用BE-SONOS的2T单元NOR架构包括具有存取晶体管的存储单元，存储晶体管具有存取栅极和存储晶体管，存储晶体管具有串联布置在相应的位线和多条参考线之一中的存储栅极。存储单元中的存储晶体管包括半导体本体，其包括具有沟道表面的沟道和在存储器栅极和沟道表面之间的电荷存储电介质叠层。电介质堆叠包括接触栅极（用于栅极注入隧道）和沟道表面之一（用于沟道注入隧道）的带隙工程化的隧道电介质层。存储单元的电介质叠层还包括在隧道介电层上的电荷捕获电介质层和阻挡电介质层。

98. 发明授权

US08860124B2 Depletion-mode charge-trapping flash device 有权
标题翻译：消耗模式充电陷阱闪光装置
公开(公告)号：US08860124B2
公开(公告)日：2014-10-14
申请号：US12553758
申请日：2009-09-03
申请人： Hang-Ting Lue , Yi-Hsuan Hsiao
发明人： Hang-Ting Lue , Yi-Hsuan Hsiao
IPC分类号： H01L29/66 , H01L27/115 , H01L29/51 , H01L29/792 , G11C16/04
CPC分类号： H01L29/792 , G11C16/0483 , H01L27/11568 , H01L29/513
摘要： A memory device includes a plurality of semiconductor lines, such as body-tied fins, on a substrate. The lines including buried-channel regions doped for depletion mode operation. A storage structure lies on the plurality of lines, including tunnel insulating layer on the channel regions of the fins, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer. A plurality of word lines overlie the storage structure and cross over the channel regions of the semiconductor lines, whereby memory cells lie at cross-points of the word lines and the semiconductor lines.
摘要翻译：存储器件在衬底上包括多个半导体线，例如体结翅片。这些线包括掺杂用于耗尽模式操作的掩埋沟道区。存储结构位于多条线上，包括鳍状物的沟道区上的隧道绝缘层，隧道绝缘层上的电荷存储层，以及电荷存储层上的阻挡绝缘层。多个字线覆盖在存储结构上并与半导体线的沟道区交叉，由此存储单元位于字线和半导体线的交叉点。

99. 发明授权

US08675381B2 Transistor having an adjustable gate resistance and semiconductor device comprising the same 有权
标题翻译：具有可调节栅极电阻的晶体管和包括其的半导体器件
公开(公告)号：US08675381B2
公开(公告)日：2014-03-18
申请号：US12839842
申请日：2010-07-20
申请人： Hang-Ting Lue , Kuo-Pin Chang
发明人： Hang-Ting Lue , Kuo-Pin Chang
IPC分类号： G11C5/06
CPC分类号： G11C13/0007 , G11C11/5685 , G11C11/5692 , G11C16/0483 , G11C17/165 , G11C2013/0071 , G11C2213/15 , G11C2213/53 , G11C2213/75
摘要： A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.
摘要翻译：存储器件包括每个能够存储多个数据位的存储器单元的阵列。存储单元被布置在连接到公共源极线的存储器串中。每个存储单元包括与电阻串联连接的可编程晶体管。晶体管包括可在多个不同电阻值之间切换的栅极电介质。晶体管的阈值电压根据栅极电介质的电阻值而变化。因此，存储器单元的存储器状态可以与晶体管的电介质层的相应电阻值相关联。

100. 发明授权

US08432719B2 Three-dimensional stacked and-type flash memory structure and methods of manufacturing and operating the same hydride 有权
标题翻译：三维堆叠式闪存结构及制造和操作相同氢化物的方法
公开(公告)号：US08432719B2
公开(公告)日：2013-04-30
申请号：US13008384
申请日：2011-01-18
申请人： Hang-Ting Lue
发明人： Hang-Ting Lue
IPC分类号： G11C11/00
CPC分类号： H01L27/11556 , G11C8/16 , G11C16/0416 , H01L27/11524
摘要： A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, wherein one set of channels is sandwiched between the adjacent sets of bit lines and source lines.
摘要翻译： 3D堆叠的AND型闪速存储器结构包括以三维阵列布置的多个存储单元的水平面，并且每个水平面包括交替布置的多个字线和几个电荷俘获多层，并且相邻的字线与每个其他每个电荷捕获多层介于其间; 交替布置并垂直于水平面布置的多组位线和源极线; 以及交替布置并且垂直于水平面布置的多组绝缘柱和一组绝缘柱，其中一组通道夹在相邻的位线组和源极线之间。

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