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91. 发明申请

US20090286369A1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20090286369A1
公开(公告)日：2009-11-19
申请号：US12453676
申请日：2009-05-19
申请人： Jee-Hyun Park , Jeong-Uk Han , Jae-Min Yu , Young-Cheon Jeong , Sang-Hoon Park , Kwan-Jong Roh , Byeong-Cheol Lim , Yong-Seok Chung
发明人： Jee-Hyun Park , Jeong-Uk Han , Jae-Min Yu , Young-Cheon Jeong , Sang-Hoon Park , Kwan-Jong Roh , Byeong-Cheol Lim , Yong-Seok Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/4234 , H01L27/11568 , H01L27/11573
摘要： In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.
摘要翻译：在制造半导体器件的方法中，在衬底上形成隧道绝缘层。在隧道绝缘层上形成电荷捕获层。在电荷捕获层上形成保护层图案或模具。通过使用保护层图案或模具蚀刻电荷捕获层，在隧道绝缘层上形成电荷俘获层图案。电荷捕获层图案可以彼此间隔开。阻挡层分别形成在电荷俘获层图案上。使用保护层图案或模具在阻挡层和隧道绝缘层上形成栅电极。

92. 发明授权

US07598139B2 Single chip data processing device with embedded nonvolatile memory and method thereof 失效
标题翻译：具有嵌入式非易失性存储器的单片数据处理装置及其方法
公开(公告)号：US07598139B2
公开(公告)日：2009-10-06
申请号：US11896560
申请日：2007-09-04
申请人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
发明人： Weon-Ho Park , Sang-Soo Kim , Hyun-Khe Yoo , Sung-Chul Park , Byoung-Ho Kim , Ju-Ri Kim , Seung-Beom Yoon , Jeong-Uk Han
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/76224 , H01L21/823842 , H01L21/823857 , H01L21/823892 , H01L27/0922 , H01L27/105 , H01L27/11546
摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.
摘要翻译：描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管在多个孔的每一个内。描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围。

93. 发明授权

US07515468B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07515468B2
公开(公告)日：2009-04-07
申请号：US11600427
申请日：2006-11-16
申请人： Bo-Young Seo , Hee-Seog Jeon , Jeong-Uk Han , Sung-Taeg Kang
发明人： Bo-Young Seo , Hee-Seog Jeon , Jeong-Uk Han , Sung-Taeg Kang
IPC分类号： G11C11/34
CPC分类号： G11C16/0408 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile memory device includes a memory cell unit including a pair of memory transistors and one select transistor. The select transistor is disposed between the pair of memory transistors formed in an active region in a semiconductor substrate. Two bit lines are provided, one bit line being connected to a corresponding one of the pair of memory transistors, and the other bit line being connected to a corresponding other of the pair of memory transistors.
摘要翻译：非易失性存储器件包括具有一对存储晶体管和一个选择晶体管的存储单元单元。选择晶体管设置在形成在半导体衬底中的有源区中的一对存储晶体管之间。提供了两个位线，一个位线连接到该对存储晶体管中对应的一个位线，另一个位线连接到该对存储晶体管中的相应另一个。

94. 发明申请

US20090059664A1 Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same 有权
标题翻译：电可擦除可编程只读存储器（EEPROM）单元及其形成和读取方法
公开(公告)号：US20090059664A1
公开(公告)日：2009-03-05
申请号：US12192839
申请日：2008-08-15
申请人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Jung-Ho Moon , Soung-Youb Ha
发明人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Jung-Ho Moon , Soung-Youb Ha
IPC分类号： G11C16/04 , G11C7/00 , G11C16/06 , H01L21/336
CPC分类号： G11C16/0433 , G11C16/26 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.
摘要翻译：在EEPROM单元中读取数据的方法中，用于读取的位线电压被施加到包括存储晶体管和选择晶体管的EEPROM单元。第一电压被施加到存储晶体管的感测线。大于第一电压的第二电压被施加到选择晶体管的字线。将通过EEPROM单元的电流与预定的参考电流进行比较，以读取存储在EEPROM单元中的数据。可以在擦除状态下增加EEPROM单元的通电池电流，并且可以容易地区分单元中的数据。

95. 发明授权

US07492002B2 Non-volatile memory device with a select gate electrode and a control gate electrode formed on a floating gate 失效
标题翻译：具有选择栅电极和形成在浮栅上的控制栅电极的非易失性存储器件
公开(公告)号：US07492002B2
公开(公告)日：2009-02-17
申请号：US11323355
申请日：2005-12-30
申请人： Hee-Seog Jeon , Seung-Beom Yoon , Jeong-Uk Han , Yong-Tae Kim
发明人： Hee-Seog Jeon , Seung-Beom Yoon , Jeong-Uk Han , Yong-Tae Kim
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115 , H01L27/11524 , H01L29/42328
摘要： A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.
摘要翻译：非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极通过隧道绝缘层引起电荷隧穿。选择栅电极与控制栅电极绝缘。根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

96. 发明授权

US07429766B2 Split gate type nonvolatile memory device 失效
标题翻译：分闸式非易失性存储器件
公开(公告)号：US07429766B2
公开(公告)日：2008-09-30
申请号：US11413640
申请日：2006-04-28
申请人： Hee-Seog Jeon , Seung-Beom Yoon , Jeong-Uk Han , Yong-Tae Kim
发明人： Hee-Seog Jeon , Seung-Beom Yoon , Jeong-Uk Han , Yong-Tae Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： In a split gate type nonvolatile memory device, a supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.
摘要翻译：在分离栅型非易失性存储器件中，辅助层图案设置在半导体衬底的源极区域上。由于源区域由于存在辅助层图案而垂直延伸，因此可以增加浮置栅极与源区域和辅助层图案重叠的区域的面积。因此，形成在源极和浮置栅极之间的电容器的电容增加，使得非易失性存储器件可以在低电压电平下执行编程/擦除操作。

97. 发明申请

US20080093646A1 Non-volatile memory device and method for fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080093646A1
公开(公告)日：2008-04-24
申请号：US11602075
申请日：2006-11-20
申请人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Young Ho Kim , Myung-Jo Chun
发明人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Young Ho Kim , Myung-Jo Chun
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , H01L29/66825
摘要： A non-volatile memory device comprises a semiconductor substrate having source/drain regions formed at both ends of a channel region, a gate structure forming an offset region by being separated a predetermined distance from the source region and comprising a charge accumulation region and a control gate sequentially deposited in the channel region to at least partially overlap the drain region, and a spacer arranged at each of both side walls of the gate structure. A threshold voltage value of the offset region changes depending on a dielectric constant of the spacer.
摘要翻译：一种非易失性存储器件包括：半导体衬底，其具有形成在沟道区两端的源极/漏极区;栅极结构，通过与源极区隔开预定的距离而形成偏移区，并且包括电荷累积区和控制顺序地沉积在沟道区域中以与漏极区域至少部分重叠的栅极以及布置在栅极结构的两个侧壁中的每一个侧壁处的间隔物。偏移区域的阈值电压值根据间隔物的介电常数而变化。

98. 发明申请

US20080080244A1 Non-volatile memory devices including local control gates on multiple isolated well regions and related methods and systems 有权
标题翻译：非易失性存储器件包括多个隔离阱区域上的本地控制栅极以及相关的方法和系统
公开(公告)号：US20080080244A1
公开(公告)日：2008-04-03
申请号：US11818238
申请日：2007-06-13
申请人： Yong-Kyu Lee , Myung-Jo Chun , Young-Ho Kim , Hee-Seog Jeon , Jeong-Uk Han
发明人： Yong-Kyu Lee , Myung-Jo Chun , Young-Ho Kim , Hee-Seog Jeon , Jeong-Uk Han
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/0433 , G11C8/10 , G11C16/08 , H01L27/115 , H01L27/11526 , H01L27/11534
摘要： A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided on the second well. A local control gate line may be electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor may be electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor may be configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the group selection transistor. Related methods and systems are also discussed.
摘要翻译：非易失性集成电路存储器件可以包括具有相同导电类型的第一和第二电隔离阱的半导体衬底。可以在第一阱上提供第一多个非易失性存储单元晶体管，并且可以在第二阱上提供第二多个非易失性存储单元晶体管。本地控制栅极线可以与第一和第二多个非易失性存储单元晶体管电耦合，并且组选择晶体管可以电耦合在本地控制栅极线和全局控制栅极线之间。更具体地，组选择晶体管可以被配置为响应于施加到组选择晶体管的栅极的组选择栅极信号来电耦合和去耦合本地控制栅极线和全局控制栅极线。还讨论了相关方法和系统。

99. 发明申请

US20080001204A1 Non-volatile memory device and method for fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080001204A1
公开(公告)日：2008-01-03
申请号：US11647711
申请日：2006-12-29
申请人： Yong-Kyu Lee , Hee-Seog Jeon , Jeong-Uk Han
发明人： Yong-Kyu Lee , Hee-Seog Jeon , Jeong-Uk Han
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , G11C16/0433 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory device and a method for fabricating the non-volatile memory device. The non-volatile memory device includes a memory cell located in a first conductive region and has a memory transistor, a selection transistor and a high voltage switching device located in a second conductive region close to the first conductive region. The memory cell is controlled by the high voltage switching device. At least one of the high voltage switching device, the memory transistor, or the selection transistor has a recessed channel region.
摘要翻译：一种非易失性存储器件和用于制造非易失性存储器件的方法。非易失性存储器件包括位于第一导电区域中的存储单元，并且具有位于靠近第一导电区域的第二导电区域中的存储晶体管，选择晶体管和高压开关器件。存储单元由高电压开关装置控制。高压开关器件，存储晶体管或选择晶体管中的至少一个具有凹陷沟道区域。

100. 发明申请

US20070126048A1 Semiconductor device and method of forming the same 失效
标题翻译：半导体器件及其形成方法
公开(公告)号：US20070126048A1
公开(公告)日：2007-06-07
申请号：US11600499
申请日：2006-11-16
申请人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang
发明人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang
IPC分类号： H01L29/94
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/66825 , Y10S257/90
摘要： There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.
摘要翻译：提供了一种半导体器件及其形成方法。半导体器件包括存储器件和自对准选择器件。在自对准选择装置和存储装置之间形成浮点。

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