专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20130057991A1 SILICON CONTROLLED RECTIFIER STRUCTURE WITH IMPROVED JUNCTION BREAKDOWN AND LEAKAGE CONTROL 有权
标题翻译：硅控制整流器结构具有改进的断路和漏电控制
公开(公告)号：US20130057991A1
公开(公告)日：2013-03-07
申请号：US13226838
申请日：2011-09-07
申请人： Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Alain Loiseau
发明人： Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Alain Loiseau
IPC分类号： H02H9/04 , H01L21/332 , G06F17/50 , H01L29/74
CPC分类号： H01L29/66363 , G06F17/50 , H01L27/0262 , H01L29/74 , H01L29/7436 , H02H9/04
摘要： Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.
摘要翻译：可控硅整流器的器件结构和设计结构，以及制造可控硅整流器的方法。器件结构包括设置在包含可控硅整流器的第一和第二p-n结的器件区域的顶表面上的不同材料的第一和第二层。第一层横向定位在与第一p-n结垂直对准的顶表面上。第二层横向定位在与第二p-n结垂直对准的器件区域的顶表面上。包括第二层的材料具有比包含第一层的材料更高的电阻率。

92. 发明授权

US08299533B2 Vertical NPNP structure in a triple well CMOS process 有权
标题翻译：三阱CMOS工艺中的垂直NPNP结构
公开(公告)号：US08299533B2
公开(公告)日：2012-10-30
申请号：US12954155
申请日：2010-11-24
申请人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L23/62
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

93. 发明申请

US20120146150A1 SELF-PROTECTED ELECTROSTATIC DISCHARGE FIELD EFFECT TRANSISTOR (SPESDFET), AN INTEGRATED CIRCUIT INCORPORATING THE SPESDFET AS AN INPUT/OUTPUT (I/O) PAD DRIVER AND ASSOCIATED METHODS OF FORMING THE SPESDFET AND THE INTEGRATED CIRCUIT 有权
标题翻译：自保护静电放电场效应晶体管（SPESDFET），集成电路作为输入/输出（I / O）PAD驱动器的SPESDFET和相关的形成SPESDFET和集成电路的方法
公开(公告)号：US20120146150A1
公开(公告)日：2012-06-14
申请号：US12967114
申请日：2010-12-14
申请人： Robert J. Gauthier, JR. , Mahender Kumar , Junjun Li , Dustin K. Slisher
发明人： Robert J. Gauthier, JR. , Mahender Kumar , Junjun Li , Dustin K. Slisher
IPC分类号： H01L23/62 , H01L21/336
CPC分类号： H01L23/60 , H01L27/0266 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.
摘要翻译：公开了自保护静电放电场效应晶体管（SPESDFET）的实施例。在SPESDFET实施例中，电阻区域横向定位在深源极/漏极区域的两个离散部分之间：与沟道区域相邻的第一部分和接触的第二部分。深源极/漏极区域的第二部分被硅化，但是与沟道区域和电阻区域相邻的第一部分是非硅化的。另外，栅极结构可以是硅化的或非硅化的。利用这种配置，所公开的SPESDFET提供强大的ESD保护，而不消耗额外的面积，而不改变基本FET设计（例如，不增加深源/漏区和沟道区之间的距离）。还公开了将SPESDFET作为输入/输出（I / O）焊盘驱动器和用于形成SPESDFET和集成电路的方法实施例的集成电路的实施例。

94. 发明申请

US20120126285A1 Vertical NPNP Structure In a Triple Well CMOS Process 有权
标题翻译：三井CMOS工艺中的垂直NPNP结构
公开(公告)号：US20120126285A1
公开(公告)日：2012-05-24
申请号：US12954155
申请日：2010-11-24
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/74 , G06F17/50 , H01L21/332
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

95. 发明授权

US08039868B2 Structure and method for an electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure 有权
标题翻译：静电放电（ESD）可控硅整流（SCR）结构的结构和方法
公开(公告)号：US08039868B2
公开(公告)日：2011-10-18
申请号：US12342228
申请日：2008-12-23
申请人： Robert J. Gauthier, Jr. , Junjun Li , Aniket Srivastava
发明人： Robert J. Gauthier, Jr. , Junjun Li , Aniket Srivastava
IPC分类号： H01L29/72 , H01L29/74
CPC分类号： H01L29/66386 , H01L24/06 , H01L27/0262 , H01L29/74 , H01L29/7436 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. Further, the first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括形成在衬底中的第一和第二可控硅整流器（SCR）。此外，第一和第二SCR各自包括在第一和第二SCR之间共同共享的至少一个部件。

96. 发明申请

US20090086391A1 Stacked Power Clamp Having a BigFET Gate Pull-Up Circuit 失效
标题翻译：具有BigFET门上拉电路的堆叠电源钳位
公开(公告)号：US20090086391A1
公开(公告)日：2009-04-02
申请号：US11865820
申请日：2007-10-02
申请人： Robert J. Gauthier, JR. , Junjun Li
发明人： Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H02H9/00
CPC分类号： H01L27/0285
摘要： An electronic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs and a triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.
摘要翻译：一种用于保护集成电路芯片免受ESD事件的电子放电（ESD）保护电路。 ESD保护电路包括一叠BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及响应于ESD事件触发BigFET栅极驱动器来驱动BigFET的栅极。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。

97. 发明授权

US08987073B2 Self-protected metal-oxide-semiconductor field-effect transistor 有权
标题翻译：自保护金属氧化物半导体场效应晶体管
公开(公告)号：US08987073B2
公开(公告)日：2015-03-24
申请号：US13546509
申请日：2012-07-11
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L21/00 , H01L21/84 , H01L27/02 , H01L27/12 , H01L29/66
CPC分类号： H01L23/60 , H01L21/84 , H01L27/0251 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.
摘要翻译：金属氧化物半导体场效应晶体管的器件结构，设计结构和制造方法。栅极结构形成在衬底的顶表面上。第一和第二沟槽形成在与栅极结构的侧壁相邻的衬底中。第二沟槽横向形成在第一沟槽和第一侧壁之间。第一和第二外延层分别形成在第一和第二沟槽中。形成到作为漏极的第一外延层的接触。第二沟槽中的第二外延层不接触，使得第二外延层用作镇流电阻器。

98. 发明授权

US08796731B2 Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure 有权
标题翻译：低泄漏，低电容静电放电（ESD）硅控制背光（SCR），制造方法和设计结构
公开(公告)号：US08796731B2
公开(公告)日：2014-08-05
申请号：US12859801
申请日：2010-08-20
申请人： Michel J. Abou-Khalil , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
发明人： Michel J. Abou-Khalil , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
IPC分类号： H01L29/861
CPC分类号： H01L29/7412 , H01L27/0262
摘要： A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.
摘要翻译：提供了低泄漏，低电容二极管的触发静电放电（ESD）硅控整流器（SCR），制造方法和设计结构。该方法包括在绝缘体层上提供硅膜。该方法还包括形成从硅层的上侧延伸到绝缘体层的隔离区域。该方法还包括在硅层中形成一个或多个二极管，包括形成在由隔离区界定的阱中的p +区和n +区。隔离区域沿垂直方向隔离一个或多个二极管，并且绝缘体层在水平方向上将一个或多个二极管与下面的P或N型衬底隔离。

99. 发明授权

US08730624B2 Electrostatic discharge power clamp with a JFET based RC trigger circuit 有权
标题翻译：具有基于JFET的RC触发电路的静电放电电源钳位
公开(公告)号：US08730624B2
公开(公告)日：2014-05-20
申请号：US13076625
申请日：2011-03-31
申请人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.
摘要翻译： ESD功率钳位电路及ESD保护方法。 ESD功率钳位电路包括：耦合到电阻/电容（RC）网络的功率钳位装置，RC网络包括作为RC网络的电容元件的电容器和被配置为可变的一个或多个结场效应晶体管（JFET）电阻器作为RC网络的电阻元件。

100. 发明申请

US20140015053A1 SELF-PROTECTED METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR 有权
标题翻译：自保护金属氧化物半导体场效应晶体管
公开(公告)号：US20140015053A1
公开(公告)日：2014-01-16
申请号：US13546509
申请日：2012-07-11
申请人： James P. Di Sarro , Robert J. Gauthier, JR. , Junjun Li
发明人： James P. Di Sarro , Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L23/60 , H01L21/84 , H01L27/0251 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.
摘要翻译：金属氧化物半导体场效应晶体管的器件结构，设计结构和制造方法。栅极结构形成在衬底的顶表面上。第一和第二沟槽形成在与栅极结构的侧壁相邻的衬底中。第二沟槽横向形成在第一沟槽和第一侧壁之间。第一和第二外延层分别形成在第一和第二沟槽中。形成到作为漏极的第一外延层的接触。第二沟槽中的第二外延层不接触，使得第二外延层用作镇流电阻器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式