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91. 发明申请

US20120179876A1 Cache-Based Speculation of Stores Following Synchronizing Operations 失效
标题翻译：基于缓存的商店跟随同步操作
公开(公告)号：US20120179876A1
公开(公告)日：2012-07-12
申请号：US12985590
申请日：2011-01-06
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0837 , G06F12/0895
摘要： A method of processing store requests in a data processing system includes enqueuing a store request in a store queue of a cache memory of the data processing system. The store request identifies a target memory block by a target address and specifies store data. While the store request and a barrier request older than the store request are enqueued in the store queue, a read-claim machine of the cache memory is dispatched to acquire coherence ownership of target memory block of the store request. After coherence ownership of the target memory block is acquired and the barrier request has been retired from the store queue, a cache array of the cache memory is updated with the store data.
摘要翻译：在数据处理系统中处理存储请求的方法包括在数据处理系统的高速缓存存储器的存储队列中引入存储请求。存储请求通过目标地址识别目标存储器块并指定存储数据。当存储请求和存储请求之前的屏障请求在存储队列中排队时，调度高速缓冲存储器的读取机器以获取存储请求的目标存储器块的一致性所有权。在获取目标存储器块的一致性所有权并且屏障请求已经从存储队列中退出之后，用存储数据更新高速缓冲存储器的高速缓存阵列。

92. 发明授权

US08131935B2 Virtual barrier synchronization cache 失效
标题翻译：虚拟障碍同步缓存
公开(公告)号：US08131935B2
公开(公告)日：2012-03-06
申请号：US12419364
申请日：2009-04-07
申请人： Ravi K. Arimilli , Guy L. Guthrie , Robert A. Cargnoni , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , Robert A. Cargnoni , William J. Starke , Derek E. Williams
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0811 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.
摘要翻译：数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元，访问系统内存的虚拟屏障同步区域。多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括从系统存储器的虚拟屏障同步区域缓存VBSR行的缓存阵列和高速缓存控制器。高速缓存控制器响应于来自处理器核心的存储请求来更新特定VBSR线路，通过发送来同时保存特定VBSR线路的副本的多个处理单元中的彼此之间的高速缓存阵列的非阻塞更新互连结构上的VBSR更新命令。

93. 发明授权

US08117397B2 Victim cache line selection 有权
标题翻译：受害者缓存行选择
公开(公告)号：US08117397B2
公开(公告)日：2012-02-14
申请号：US12335809
申请日：2008-12-16
申请人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0817 , G06F12/0862 , G06F12/0897 , Y02D10/13
摘要： A cache memory includes a cache array including a plurality of congruence classes each containing a plurality of cache lines, where each cache line belongs to one of multiple classes which include at least a first class and a second class. The cache memory also includes a cache directory of the cache array that indicates class membership. The cache memory further includes a cache controller that selects a victim cache line for eviction from a congruence class. If the congruence class contains a cache line belonging to the second class, the cache controller preferentially selects as the victim cache line a cache line of the congruence class belonging to the second class based upon access order. If the congruence class contains no cache line belonging to the second class, the cache controller selects as the victim cache line a cache line belonging to the first class based upon access order.
摘要翻译：高速缓存存储器包括包含多个等同类的高速缓存阵列，每个级别包含多条高速缓存行，其中每条高速缓存行属于至少包括第一类和第二类的多个类中的一个。缓存存储器还包括指示类成员资格的高速缓存阵列的高速缓存目录。高速缓冲存储器还包括高速缓存控制器，其选择用于从同余类驱逐的受害缓存行。如果同余类包含属于第二类的高速缓存行，则高速缓存控制器基于访问顺序优先选择属于第二类的同余类的高速缓存行作为受害缓存行。如果同余类不包含属于第二类的高速缓存行，则高速缓存控制器基于访问顺序选择属于第一类的高速缓存行作为受害缓存行。

94. 发明授权

US07944932B2 Interconnect fabric for a data processing system 有权
标题翻译：用于数据处理系统的互连结构
公开(公告)号：US07944932B2
公开(公告)日：2011-05-17
申请号：US12060751
申请日：2008-04-01
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke
IPC分类号： H04L12/28 , G06F15/173 , G06F15/76 , G06F15/00
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts operations received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units.
摘要翻译：数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。多个处理单元中的每一个包括互连逻辑，耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个处理单元接收的操作广播到多个处理单元中的一个或多个处理单位。

95. 发明授权

US07584331B2 Data processing system and method for selectively updating an invalid coherency state in response to snooping a castout 有权
标题翻译：数据处理系统和方法，用于有选择地更新无效的一致性状态以响应窥探倾倒
公开(公告)号：US07584331B2
公开(公告)日：2009-09-01
申请号：US11146443
申请日：2005-06-06
申请人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813
摘要： In an entry of a first cache memory within a first coherency domain of a data processing system including at least first and second coherency domains, a coherency state field is set to a first state that indicates that an associated address tag is valid, an associated storage location does not contain valid data, and a memory block identified by the address tag is likely cached outside the first coherency domain. In response to snooping a castout operation, the first cache memory determines if the castout operation hits in the entry and, if so, updates the coherency state field from the first state to a second state indicating that the associated address tag is invalid.
摘要翻译：在包括至少第一和第二相干域的数据处理系统的第一相关域内的第一高速缓存存储器的条目中，一致性状态字段被设置为指示相关联的地址标签有效的第一状态，相关联的存储位置不包含有效数据，并且由地址标签标识的存储器块可能在第一个一致性域之外缓存。响应于窥探移除操作，第一高速缓存存储器确定该转义操作是否在条目中命中，如果是，则将相关性状态字段从第一状态更新为指示相关联的地址标签无效的第二状态。

96. 发明授权

US07577797B2 Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response 失效
标题翻译：数据处理系统，缓存系统和基于组合响应精确形成无效一致性状态的方法
公开(公告)号：US07577797B2
公开(公告)日：2009-08-18
申请号：US11388016
申请日：2006-03-23
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain includes a system memory controller for a system memory and a first processing unit having a first cache memory. The second coherency domain includes a second processing unit having a second cache memory. In the first cache memory, a coherency state field associated with a storage location and an address tag is set to a first coherency state. In response to snooping an exclusive access request specifying a target address matching the address tag, the first cache memory provides a first partial response to the exclusive access request based at least in part upon the first coherency state. In response to snooping the exclusive access request, the memory controller determines whether it is responsible for the target address and provides a second partial response to the exclusive access request based at least in part upon an outcome of the determination. At least the first and second partial responses are accumulated to obtain a combined response for the exclusive access request. The combined response includes an indication of whether or not a highest point of coherency and a memory controller of a home system memory for the target address reside within a same coherency domain. The first cache memory updates the coherency state field from the first coherency state to a second coherency state in response to the indication in the combined response.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。第一相干域包括用于系统存储器的系统存储器控制器和具有第一高速缓冲存储器的第一处理单元。第二相关域包括具有第二高速缓冲存储器的第二处理单元。在第一缓存存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为第一相关性状态。响应于窥探专用访问请求，指定与地址标签匹配的目标地址，第一高速缓存存储器至少部分地基于第一相关性状态向独占访问请求提供第一部分响应。响应于窥探专用访问请求，存储器控制器至少部分地基于确定的结果来确定它是否对目标地址负责并且向独占访问请求提供第二部分响应。至少第一和第二部分响应被累积以获得专用访问请求的组合响应。组合响应包括关于目标地址的家庭系统存储器的最高点的一致性和存储器控制器是否位于相同的一致性域内的指示。响应于组合响应中的指示，第一缓存存储器将相关性状态字段从第一相关性状态更新为第二相关性状态。

97. 发明申请

US20090198920A1 Processing Units Within a Multiprocessor System Adapted to Support Memory Locks 审中-公开
标题翻译：适用于支持内存锁的多处理器系统中的处理单元
公开(公告)号：US20090198920A1
公开(公告)日：2009-08-06
申请号：US12024234
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F15/16 , G06F9/3004 , G06F9/30087 , G06F9/526
摘要： A processing unit within a multiprocessor system adapted to support memory locks is disclosed. In response to a request for accessing a data block being denied when a lock control section of the data block has been set by a memory controller, a timer countdown is started within a processing unit within a multiprocessor system. The requesting processing unit can relinquish the access request once the timer countdown has reached a timeout period.
摘要翻译：公开了一种适于支持存储器锁的多处理器系统内的处理单元。响应于当由存储器控制器设置数据块的锁定控制部分时访问被拒绝的数据块的请求，在多处理器系统内的处理单元内启动定时器倒计时。一旦定时器倒计时达到超时时间，请求处理单元可以放弃访问请求。

98. 发明申请

US20090198916A1 Method and Apparatus for Supporting Low-Overhead Memory Locks Within a Multiprocessor System 审中-公开
标题翻译：用于支持多处理器系统内的低成本内存锁的方法和装置
公开(公告)号：US20090198916A1
公开(公告)日：2009-08-06
申请号：US12024223
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Edward J. Seminaro , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Edward J. Seminaro , William J. Starke
IPC分类号： G06F12/14
CPC分类号： G06F12/1466 , G06F9/3004 , G06F9/30087
摘要： A method for supporting low-overhead memory locks within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is ignored. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.
摘要翻译：公开了一种用于支持多处理器系统内的低开销存储器锁的方法。锁控制部分最初被分配给多处理器系统的系统存储器内的数据块。响应于由多处理器系统内的处理单元访问数据块的请求，由存储器控制器确定数据块的锁定控制部分是否已被设置。如果已经设置了数据块的锁定控制部分，则忽略访问数据块的请求。否则，如果未设置数据块的锁定控制部分，则设置数据块的锁定控制部分，并且允许访问数据块的请求。

99. 发明授权

US07483422B2 Data processing system, method and interconnect fabric for selective link information allocation in a data processing system 失效
标题翻译：数据处理系统，数据处理系统中选择性链路信息分配的方法和互连结构
公开(公告)号：US07483422B2
公开(公告)日：2009-01-27
申请号：US11055366
申请日：2005-02-10
申请人： James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
发明人： James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： H04L12/28 , G06F15/00 , G06F13/00 , G06F12/00
CPC分类号： G06F15/177 , G06F12/0831 , G06F12/0897
摘要： A data processing system includes a plurality of processing units coupled for communication by a communication link and a configuration register. The configuration register has a plurality of different settings each corresponding to a respective one of a plurality of different link information allocations. Information is communicated over the communication link in accordance with a particular link information allocation among the plurality of link information allocations determined by a respective setting of the configuration register.
摘要翻译：数据处理系统包括多个处理单元，其被耦合以通过通信链路和配置寄存器进行通信。配置寄存器具有多个不同的设置，每个对应于多个不同链接信息分配中的相应一个。根据通过配置寄存器的相应设置确定的多个链路信息分配中的特定链路信息分配，通过通信链路传送信息。

100. 发明申请

US20090006766A1 DATA PROCESSING SYSTEM AND METHOD FOR PREDICTIVELY SELECTING A SCOPE OF BROADCAST OF AN OPERATION UTILIZING A HISTORY-BASED PREDICTION 审中-公开
标题翻译：数据处理系统和方法，用于预测性地选择使用基于历史的预测操作的广播范围
公开(公告)号：US20090006766A1
公开(公告)日：2009-01-01
申请号：US11957996
申请日：2007-12-17
申请人： BENJIMAN L. GOODMAN , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： BENJIMAN L. GOODMAN , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , G06F2212/507
摘要： According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.
摘要翻译：根据数据处理的方法，保持预测器，其指示在数据处理系统的互连上发送的一个或多个先前操作的广播的历史范围。通过参考预测器预测性地选择后续操作的广播范围。

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