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    • 95. 发明授权
    • Adjustable alarm device for sliding doors and windows
    • 用于滑动门窗的可调报警装置
    • US06943686B2
    • 2005-09-13
    • US10313017
    • 2002-12-06
    • Robert Allen
    • Robert Allen
    • G08B13/08
    • G08B13/08
    • An adjustable alarm device for windows and doors is installed between the door or window frame and the door or window sash. The longitudinal axis of the alarm device is preferably horizontal. When engaged, movement of the door or window in an open direction will activate the alarm. The body of the alarm device is elongate, tubular and telescoping. The body comprises an outer tube that receives an inner tube. The body of the alarm device may be locked in an extended position by way of a cam mounted on the inner tube and positioned within the body so that when the inner and outer tubes of the body are twisted about their longitudinal axis, the cam body will engage the inner surface of the outer tube in a releasable frictional locking engagement. The alarm device is coupled to one end of the inner tube.
    • 门和门的可调报警装置安装在门框或窗框与门或窗扇之间。 报警装置的纵向轴线最好是水平的。 当接合时,门或窗在开启方向的移动将激活报警。 报警装置的主体是细长的,管状的和伸缩的。 主体包括接收内管的外管。 警报装置的主体可以通过安装在内管上的凸轮锁定在延伸位置并且定位在主体内,使得当主体的内管和外管围绕其纵向轴线扭转时,凸轮体将 以可释放的摩擦锁定接合方式将外管的内表面接合。 报警装置连接到内管的一端。
    • 96. 发明申请
    • THE USE OF A LAYOUT-OPTIMIZATION TOOL TO INCREASE THE YIELD AND RELIABILITY OF VLSI DESIGNS
    • 使用布局优化工具来增加VLSI设计的可靠性和可靠性
    • US20050048677A1
    • 2005-03-03
    • US10604987
    • 2003-08-29
    • Robert AllenJason HibbelerGustavo Tellez
    • Robert AllenJason HibbelerGustavo Tellez
    • G06F17/50H01L21/00
    • G06F17/5068
    • The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. Next, the invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via. The invention repeats the foregoing processing in the direction perpendicular to the first. The invention can also be used to eliminate certain undesirable structures such as stacked vias or can be used to fix other problems such as insufficient via-to-via spacing. The invention then adds the redundant vias to the integrated circuit design, according to output produced by the optimizer.
    • 本发明提供了一种用于优化集成电路设计中的冗余通孔的布置的方法和结构。 本发明首先通过确定哪些通孔没有冗余通孔来定位目标通孔。 然后,本发明在目标通孔上或附近绘制标记物形状。 标记形状仅在每个目标通孔的水平或垂直方向绘制。 接下来,本发明同时将第一方向上的所有标记形状扩展到预定长度,或者直到标记形状达到接地规则的极限。 在扩展期间,不同的标记形状将被扩展到不同的长度。 本发明确定哪些标记形状被充分扩展以形成有效的冗余通路以产生第一组潜在的冗余通孔,并且本发明消除了不能充分扩展以形成有效的冗余通路的标记形状。 本发明在垂直于第一方向的方向上重复上述处理。 本发明还可以用于消除某些不希望的结构,例如堆叠的通孔,或者可以用于固定其它问题,例如通孔间距不足。 然后,根据优化器产生的输出,本发明将冗余通孔添加到集成电路设计中。