专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20080052458A1 NON-VOLATILE, ELECTRICALLY-PROGRAMMABLE MEMORY 有权
标题翻译：非易失性，电可编程存储器
公开(公告)号：US20080052458A1
公开(公告)日：2008-02-28
申请号：US11844465
申请日：2007-08-24
申请人： Rino Micheloni , Roberto Ravasio
发明人： Rino Micheloni , Roberto Ravasio
IPC分类号： G06F12/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5641
摘要： A solid-state mass storage device is provided. The solid-state mass storage device defines a storage area adapted to store data; the storage area is adapted to be exploited for storing data with a first storage density at a first data transfer speed. The storage area includes at least a first storage area portion and a second storage area portion. The solid-state mass storage device further includes accessing logic adapted to exploit the first storage area portion for storing data with a second storage density at a second data transfer speed, and adapted to exploit the second storage area portion for storing data with a third storage density and a third data transfer speed. The second storage density is lower than the third storage density, which is in turn lower than or equal to the first storage density; the second data transfer speed is higher than the third data transfer speed, which is in turn higher than or equal to the first data transfer speed.
摘要翻译：提供固态大容量存储装置。固态大容量存储装置定义适于存储数据的存储区域; 存储区域适于被利用以以第一数据传送速度存储具有第一存储密度的数据。存储区域至少包括第一存储区域部分和第二存储区域部分。固体大容量存储装置还包括访问逻辑，其适于利用第一存储区域部分以第二数据传输速度存储具有第二存储密度的数据，并且适于利用第二存储区域部分来存储具有第三存储器的数据密度和第三数据传输速度。第二储存密度低于第三储存密度，其又低于或等于第一储存密度; 第二数据传送速度高于第三数据传送速度，其又高于或等于第一数据传送速度。

92. 发明申请

US20080049521A1 METHOD FOR COMPACTING THE ERASED THRESHOLD VOLTAGE DISTRIBUTION OF FLASH MEMORY DEVICES DURING WRITING OPERATIONS 有权
标题翻译：写入操作期间闪存存储器件的擦除阈值电压分配方法
公开(公告)号：US20080049521A1
公开(公告)日：2008-02-28
申请号：US11844480
申请日：2007-08-24
申请人： Rino Micheloni , Luca Crippa , Roberto Ravasio , Federico Pio
发明人： Rino Micheloni , Luca Crippa , Roberto Ravasio , Federico Pio
IPC分类号： G11C16/04
CPC分类号： G11C16/344
摘要： A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.
摘要翻译：一种用于操作闪存设备的方法。存储器件包括存储器单元矩阵，每个存储器单元具有限定存储在存储器单元中的值的可编程阈值电压。该方法包括以下步骤：擦除存储器单元块，以及在预定的压缩范围内压缩块的存储单元的阈值电压，其中压缩步骤包括：选择块写入的至少一个第一存储单元目标值将块的存储器单元的子集的阈值电压恢复到压缩范围，该子集包括与至少一个第一存储器相邻的块的至少一个第一存储器单元和/或至少一个第二存储器单元细胞; 并且至少部分地将目标值写入至少一个第一存储单元。

93. 发明授权

US07260005B2 Data bus architecture for a semiconductor memory 有权
标题翻译：半导体存储器的数据总线架构
公开(公告)号：US07260005B2
公开(公告)日：2007-08-21
申请号：US11281932
申请日：2005-11-17
申请人： Luca Crippa , Miriam Sangalli , Rino Micheloni
发明人： Luca Crippa , Miriam Sangalli , Rino Micheloni
IPC分类号： G11C7/00
CPC分类号： G11C7/10 , G11C7/08 , G11C7/1048
摘要： A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits isolates an associated signal line from the output of the corresponding sense amplifier at least during an evaluating phase of the datum stored in the memory cell. The signal lines include at least two groups of signal lines, arranged such that coupling capacitances between the lines of the first group and the lines of the second group are substantially negligible. The precharging circuit precharges the first group of signal lines to a first voltage level and the second group of signal lines to a second voltage level.
摘要翻译：提供了包括存储单元，读出放大器，信号线，隔离电路和预充电电路的半导体存储器件。每个信号线耦合到读出放大器中的至少一个的输出，并且每个隔离电路至少在存储在存储单元中的数据的评估阶段期间将相关联的信号线与对应的读出放大器的输出隔离。信号线包括至少两组信号线，其布置成使得第一组的线和第二组的线之间的耦合电容基本上可忽略。预充电电路将第一组信号线预充电到第一电压电平，将第二组信号线预充电到第二电压电平。

94. 发明申请

US20070164811A1 MULTISTAGE REGULATOR FOR CHARGE-PUMP BOOSTED VOLTAGE APPLICATIONS, NOT REQUIRING INTEGRATION OF DEDICATED HIGH VOLTAGE HIGH SIDE TRANSISTORS 有权
标题翻译：用于充电泵升压电压应用的多级稳压器，不需要集成高压高压侧晶体管
公开(公告)号：US20070164811A1
公开(公告)日：2007-07-19
申请号：US11460370
申请日：2006-07-27
申请人： Luca Crippa , Miriam Sangalli , Giancarlo Ragone , Rino Micheloni
发明人： Luca Crippa , Miriam Sangalli , Giancarlo Ragone , Rino Micheloni
IPC分类号： G05F1/10
CPC分类号： G11C5/145 , G11C16/30
摘要： A multistage circuit for regulating the charge voltage or the discharge current of a capacitance of an integrated device at a certain charge-pump generated boosted voltage is implemented without integrating high voltage transistor structures having a type of conductivity corresponding to the same sign of the boosted voltage (high-side transistors). The multistage circuit current includes at least a first stage, and an output stage in cascade to the first stage and coupled to the capacitance. The first stage is supplied at an unboosted power supply voltage of the integrated device, and the output stage is supplied at an unregulated charge-pump generated boosted voltage. The first stage includes a transistor having a type of conductivity corresponding to an opposite sign of the boosted voltage and of the power supply voltage. The drain of the output stage transistor is coupled to the boosted voltage either through a resistive pull-up or a voltage limiter.
摘要翻译：在一定的电荷泵产生的升压电压下，用于调节集成器件的电容的充电电压或放电电流的多级电路被实现，而不需要集成具有对应于升压电压相同符号的导电类型的高压晶体管结构（高侧晶体管）。多级电路电流包括至少第一级和级联到第一级并耦合到电容的输出级。第一级是在集成器件的未升压的电源电压下提供的，并且输出级以未调节的电荷泵产生的升压电压供电。第一级包括具有对应于升压电压和电源电压的相反符号的导电类型的晶体管。输出级晶体管的漏极通过电阻上拉或电压限制器耦合到升压电压。

95. 发明申请

US20070038852A1 CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE 有权
标题翻译：多个FLASH存储器件的配置
公开(公告)号：US20070038852A1
公开(公告)日：2007-02-15
申请号：US11460777
申请日：2006-07-28
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F15/177 , G06F9/24 , G06F9/00 , G11C16/04 , G11C11/34
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能算法。简化了测试过程中存储器件工作参数的最佳配置的识别通过在存储器件的每次上电时允许将配置位一次性处理成存储在嵌入式辅助随机存取存储器中的算法友好数据。这通过执行存储在存储器装置中的特定加电算法代码来完成嵌入式微处理器的辅助只读存储器。

96. 发明申请

US20070035995A1 METHOD OF PROGRAMMING A FOUR-LEVEL FLASH MEMORY DEVICE AND A RELATED PAGE BUFFER 审中-公开
标题翻译：编程四级闪存存储器件和相关页面缓冲器的方法
公开(公告)号：US20070035995A1
公开(公告)日：2007-02-15
申请号：US11460835
申请日：2006-07-28
申请人： Luca Crippa , Rino Micheloni
发明人： Luca Crippa , Rino Micheloni
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/10 , G11C11/5628
摘要： A four-level FLASH memory device includes an array of singularly addressable preliminarily erased memory cells, with each memory cell capable of storing a two-bit datum. When the threshold voltage of a memory cell is verified to have reached the desired distribution, the cell is read using a test read voltage smaller than or equal to the program voltage. In this situation the voltage VS on the source node is negligible, and the programmed state of the cell may be correctly verified.
摘要翻译：四级FLASH存储器件包括可单独寻址的预擦除存储器单元的阵列，每个存储器单元能够存储两位数据。当验证存储器单元的阈值电压达到期望分布时，使用小于或等于编程电压的测试读取电压来读取单元。在这种情况下，源节点上的电压V SUB可忽略不计，并且可以正确验证单元的编程状态。

97. 发明申请

US20070030732A1 Double page programming system and method 有权
标题翻译：双页编程系统和方法
公开(公告)号：US20070030732A1
公开(公告)日：2007-02-08
申请号：US11495876
申请日：2006-07-28
申请人： Rino Micheloni , Luca Crippa , Roberto Ravasio
发明人： Rino Micheloni , Luca Crippa , Roberto Ravasio
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5642 , G11C2216/14
摘要： A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The programming method includes causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state. Receiving a target value for the first data bits groups of the memory cells of the selected memory cells set. Receiving a target value for the second data bits groups of the memory cells of the selected memory cells set. After having received the target values of both the first and the second data bits groups, applying to the memory cells of the selected memory cells set a programming sequence adapted to cause the memory cells of the selected memory cells sets to be brought into a target programming state jointly determined by the target values of the first and second data bits groups.
摘要翻译：一种用于编程电可编程存储器的方法，包括布置在各自包括至少一个存储单元的可单独选择的存储单元组中的多个存储单元。编程方法包括使所设置的选定存储单元的存储单元进入预定的开始编程状态。接收所选存储器单元的存储单元的第一数据位组的目标值。接收所选存储器单元的存储单元的第二数据位组的目标值。在接收到第一和第二数据位组两者的目标值之后，将所选择的存储器单元的存储单元应用到所设置的编程顺序，以使所选择的存储单元组的存储器单元进入目标编程状态由第一和第二数据位组的目标值联合确定。

98. 发明申请

US20060164155A1 Low-ripple boosted voltage generator 审中-公开
标题翻译：低纹波升压电压发生器
公开(公告)号：US20060164155A1
公开(公告)日：2006-07-27
申请号：US11323937
申请日：2005-12-30
申请人： Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
发明人： Giancarlo Ragone , Miriam Sangalli , Rino Micheloni
IPC分类号： G05F1/10
CPC分类号： G11C5/145
摘要： The output voltage ripple of a single stage or a multi-stage charge pump may be significantly reduced by introducing in the voltage generator a cascode connected output transistor. In operation, this output transistor may be in a conduction state and may be controlled with a voltage having a smaller ripple than the voltage output by the charge pump.
摘要翻译：通过在电压发生器中引入共源共栅输出晶体管，可以显着降低单级或多级电荷泵的输出电压纹波。在操作中，该输出晶体管可以处于导通状态，并且可以通过具有比电荷泵输出的电压更小的纹波的电压来控制。

99. 发明申请

US20060010363A1 Method and system for correcting low latency errors in read and write non volatile memories, particularly of the flash type 审中-公开
标题翻译：用于校正读写非易失性存储器，特别是闪存类型的低延迟误差的方法和系统
公开(公告)号：US20060010363A1
公开(公告)日：2006-01-12
申请号：US11173896
申请日：2005-06-30
申请人： Alessia Marelli , Roberto Ravasio , Rino Micheloni
发明人： Alessia Marelli , Roberto Ravasio , Rino Micheloni
IPC分类号： H03M13/00
CPC分类号： H03M13/1555 , H03M13/152 , H03M13/6561
摘要： A method for correcting errors in multilevel memories, both of the NAND and of the NOR type provides the use of a BCH correction code made parallel by means of a coding and decoding architecture allowing the latency limits of prior art sequential solutions to be overcome. The method provides a processing with a first predetermined parallelism for the coding step, a processing with a second predetermined parallelism for the syndrome calculation and a processing with a third predetermined parallelism for calculating the error position, each parallelism being defined by a respective integer number being independent from the others.
摘要翻译：用于校正多电平存储器中的错误的方法，NAND和NOR类型都提供使用通过编码和解码架构并行制作的BCH校正码，从而可以克服现有技术顺序解决方案的等待时间限制。该方法提供用于编码步骤的第一预定并行度的处理，用于校正子计算的第二预定并行性的处理和用于计算错误位置的第三预定并行度的处理，每个并行性由相应整数定义为独立于其他人。

100. 发明申请

US20060005109A1 Method and system for correcting errors in electronic memory devices 审中-公开
标题翻译：用于校正电子存储器件中的错误的方法和系统
公开(公告)号：US20060005109A1
公开(公告)日：2006-01-05
申请号：US11169497
申请日：2005-06-29
申请人： Alessia Marelli , Roberto Ravasio , Rino Micheloni
发明人： Alessia Marelli , Roberto Ravasio , Rino Micheloni
IPC分类号： H03M13/00
CPC分类号： H03M13/152 , H03M13/1575 , H03M13/3707 , H03M13/6502
摘要： A method and system for correcting errors in multilevel memories is based upon using a combination of a BCH correction code and a Hamming correction code. The BCH correction code is used for correcting multiple errors, and the Hamming correction code is used for correcting single errors. The Hamming correction code reduces the use of the decoding blocks for the BCH correction codes, which are computationally intensive.
摘要翻译：用于校正多电平存储器中的错误的方法和系统基于使用BCH校正码和汉明校正码的组合。 BCH校正码用于校正多个错误，汉明校正码用于校正单个错误。汉明校正码减少了用于计算密集型的BCH校正码的解码块的使用。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式