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91. 发明申请

US20060263979A1 Methods of forming devices associated with semiconductor constructions 有权
标题翻译：形成与半导体结构相关的器件的方法
公开(公告)号：US20060263979A1
公开(公告)日：2006-11-23
申请号：US11131994
申请日：2005-05-18
申请人： Hasan Nejad , Gordon Haller , Thomas Figura , Ravi Iyer
发明人： Hasan Nejad , Gordon Haller , Thomas Figura , Ravi Iyer
IPC分类号： H01L21/8242 , H01L21/22 , H01L21/4763 , H01L21/44 , H01L21/302 , H01L21/38
CPC分类号： H01L27/10894 , H01L27/10876 , H01L27/10897 , Y10S439/917
摘要： The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.
摘要翻译：本发明包括形成与半导体结构相关的器件的方法。在示例性方法中，利用通常的处理步骤来形成完全硅化的凹陷阵列存取栅极和部分硅化的外围晶体管栅极。

92. 发明授权

US07101815B2 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers 有权
标题翻译：改善沉积的臭氧-TEOS硅酸盐玻璃层厚度均匀性的方法
公开(公告)号：US07101815B2
公开(公告)日：2006-09-05
申请号：US10928505
申请日：2004-08-26
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： C23C16/40
CPC分类号： H01L21/02164 , C03C17/02 , C23C16/0245 , C23C16/0272 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/31612 , H01L21/76826 , H01L21/76834 , H01L21/76837
摘要： A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 is provided, comprising placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.
摘要翻译：提供了一种通过化学气相沉积通过TEOS和O 3 3的反应沉积高度保形硅酸盐玻璃层的方法，包括将具有多个表面成分的过程中半导体晶片放置在等离子体增强化学气体沉积室。

93. 发明授权

US07078342B1 Method of forming a gate stack 失效
标题翻译：形成栅极叠层的方法
公开(公告)号：US07078342B1
公开(公告)日：2006-07-18
申请号：US09073494
申请日：1998-05-06
申请人： Pai-Hung Pan , Louie Liù , Ravi Iyer
发明人： Pai-Hung Pan , Louie Liù , Ravi Iyer
IPC分类号： H01L21/44 , H11L21/3205
CPC分类号： H01L21/28061 , H01L21/324
摘要： A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.
摘要翻译：一种用于形成栅堆叠的方法，其通过在形成期间的温度降低来最小化或消除在栅叠层形成期间对栅介质层和/或硅衬底的损坏。温度降低防止在栅极堆叠中的金属硅化物膜内形成硅团簇，这已被发现在栅极蚀刻步骤期间造成损坏。本发明还包括在栅极蚀刻步骤之前分散硅簇的方法。

94. 发明授权

US07067442B1 Method to avoid threshold voltage shift in thicker dielectric films 失效
标题翻译：避免较厚介质膜中阈值电压漂移的方法
公开(公告)号：US07067442B1
公开(公告)日：2006-06-27
申请号：US09654093
申请日：2000-08-31
申请人： Randhir P. S. Thakur , Ravi Iyer , Howard Rhodes
发明人： Randhir P. S. Thakur , Ravi Iyer , Howard Rhodes
IPC分类号： H01L21/31
CPC分类号： H01L23/3171 , H01L21/02129 , H01L21/02271 , H01L21/02304 , H01L21/02315 , H01L21/31612 , H01L21/3162 , H01L21/76828 , H01L21/76829 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
摘要翻译：提供了一种制造具有降低的阈值电压偏移的集成电路的方法。在半导体衬底上形成非导电区域，在半导体衬底上形成有源区域。有源区由非导电区分开。势垒层和电介质层沉积在非导电区域上并在有源区上方。对集成电路施加热量，导致阻挡层退火。

95. 发明申请

US20050255689A1 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers 审中-公开
标题翻译：改善沉积的臭氧-TEOS硅酸盐玻璃层厚度均匀性的方法
公开(公告)号：US20050255689A1
公开(公告)日：2005-11-17
申请号：US11175869
申请日：2005-07-06
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： C03C17/02 , C23C16/02 , C23C16/40 , C23C16/56 , H01L21/316 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02164 , C03C17/02 , C23C16/0245 , C23C16/0272 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/31612 , H01L21/76826 , H01L21/76834 , H01L21/76837
摘要： A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 is provided, comprising placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.
摘要翻译：提供了一种通过化学气相沉积通过TEOS和O 3 3的反应沉积高度保形硅酸盐玻璃层的方法，包括将具有多个表面成分的过程中半导体晶片放置在等离子体增强化学气体沉积室。

96. 发明授权

US06858526B2 Methods of forming materials between conductive electrical components, and insulating materials 失效
标题翻译：在导电电气部件和绝缘材料之间形成材料的方法
公开(公告)号：US06858526B2
公开(公告)日：2005-02-22
申请号：US09820468
申请日：2001-03-28
申请人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
发明人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763 , H01L21/302
CPC分类号： H01L23/5222 , H01L21/02115 , H01L21/02118 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02337 , H01L21/02362 , H01L21/31695 , H01L21/7682 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.
摘要翻译：本发明包括在导电元件之间形成绝缘材料的方法。在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

97. 发明申请

US20050032394A1 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers 有权
标题翻译：改善沉积的臭氧-TEOS硅酸盐玻璃层厚度均匀性的方法
公开(公告)号：US20050032394A1
公开(公告)日：2005-02-10
申请号：US10928505
申请日：2004-08-26
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： C03C17/02 , C23C16/02 , C23C16/40 , C23C16/56 , H01L21/316 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02164 , C03C17/02 , C23C16/0245 , C23C16/0272 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/31612 , H01L21/76826 , H01L21/76834 , H01L21/76837
摘要： A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 is provided, comprising placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.
摘要翻译：提供了一种通过化学气相沉积通过TEOS和O 3的反应沉积高保形硅酸盐玻璃层的方法，包括将具有多个表面成分的工艺中半导体晶片放置在等离子体增强化学气相沉积室中。

98. 发明申请

US20050023620A1 Titanium silicide boride gate electrode 有权
标题翻译：硅化钛硼化物栅电极
公开(公告)号：US20050023620A1
公开(公告)日：2005-02-03
申请号：US10926871
申请日：2004-08-26
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L21/28 , H01L21/768 , H01L29/49 , H01L29/76
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/76895
摘要： A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer. Similar methods can further be used in the formation of interconnects to connect contact regions. Gate electrode structures and interconnect structures resulting from the methods are also described. Further, in such methods and structures, the titanium boride layer may be a titanium diboride layer or a titanium boride layer having silicon incorporated therein.
摘要翻译：用于制造栅电极的方法包括提供栅极氧化层并在氧化物层上形成硼化钛层。在硼化钛层上形成绝缘体盖层，之后，由硼化钛层形成栅电极。在形成硼化钛层之前，可以在氧化物层上形成阻挡层，其中栅电极由阻挡层和硼化钛层形成。此外，在形成硼化钛层之前，可以在栅极氧化物层上形成多晶硅层，其中栅电极由硼化钛层和多晶硅层形成。此外，在形成硼化钛层之前，可以在栅极氧化物层上形成多晶硅层和在多晶硅层上形成的势垒层。然后，由多晶硅层，阻挡层和硼化钛层形成栅电极。类似的方法可以进一步用于形成互连以连接接触区域。还描述了由该方法产生的栅电极结构和互连结构。此外，在这些方法和结构中，硼化钛层可以是二硼化钛层或其中掺入硅的硼化钛层。

99. 发明授权

US06815374B2 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers 失效
标题翻译：改善沉积的臭氧-TEOS硅酸盐玻璃层厚度均匀性的方法
公开(公告)号：US06815374B2
公开(公告)日：2004-11-09
申请号：US10457298
申请日：2003-06-09
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： C23C1640
CPC分类号： H01L21/02164 , C03C17/02 , C23C16/0245 , C23C16/0272 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/31612 , H01L21/76826 , H01L21/76834 , H01L21/76837
摘要： A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.
摘要翻译：通过TEOS和O 3的反应通过化学气相沉积沉积高度保形硅酸盐玻璃层的方法包括将具有多个表面成分的工艺中半导体晶片放置在等离子体增强的化学气相沉积室中。

100. 发明授权

US06688584B2 Compound structure for reduced contact resistance 有权
公开(公告)号：US06688584B2
公开(公告)日：2004-02-10
申请号：US09858617
申请日：2001-05-16
申请人： Ravi Iyer , Yongjun Jeff Hu , Luan Tran , Brent Gilgen
发明人： Ravi Iyer , Yongjun Jeff Hu , Luan Tran , Brent Gilgen
IPC分类号： H01L2940
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/76849 , H01L21/76855 , H01L21/7687 , H01L21/76889 , H01L23/485 , H01L27/10855 , H01L28/84 , H01L28/90 , H01L29/456 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

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