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91. 发明专利

JPH0689939A SEMICONDUCTOR PRESSURE SENSOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH0689939A
公开(公告)日：1994-03-29
申请号：JP24062592
申请日：1992-09-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： IPPOSHI TAKASHI , NISHIMURA TADASHI
IPC分类号： G01L9/04 , G01L9/00 , H01L21/20 , H01L21/84 , H01L29/84
摘要： PURPOSE:To increase the insulation withstand voltage between dot seeds and wiring layers by arranging the wiring layers so that the layers can pass through spaces between adjacent dot seeds. CONSTITUTION:Wiring layers 7 are arranged so that the layers 7 can pass through spaces between adjacent dot seeds 3. The dimension of the seeds 3 is set at about, for example, 1.5-5mum and intervals between the seeds 3 are set at about 15-30mum. When the line width of the layers 7 is reduced, the layers 7 passing through spaces between the adjacent seeds 3 can be easily formed and the overlapping of the seeds 3 and the layers 7 in a plane can be prevented. Therefore, the linear distance between the layers 7 and their nearest dots 3 and, accordingly, the insulation withstand voltage between the seeds 3 and layers 7 can be increased.

92. 发明专利

JPH03239318A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03239318A
公开(公告)日：1991-10-24
申请号：JP3692990
申请日：1990-02-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： IPPOSHI TAKASHI , SUGAHARA KAZUYUKI
IPC分类号： H01L21/20 , H01L21/263 , H01L21/321 , H01L21/762
摘要： PURPOSE:To form a continuous and homogeneous single-crystal silicon layer on an insulating layer by a recrystallization operation by a method wherein, after uneven parts on the surface of a non-single-crystal layer formed on the insulating layer have been made smooth, an antireflection film is formed and a laser annealing operation is executed. CONSTITUTION:Opening parts reaching the surface of a first single-crystal semiconductor layer are formed in an insulating layer 2 formed on the surface of the first single- crystal semiconductor layer 1; a non-single-crystal semiconductor layer 3 is formed at the inside of the opening parts and on the surface of the insulating layer 2; in addition, the surface of the non-single-crystal semiconductor layer 3 is made smooth. An antireflection film 4 which is provided with a first film-thickness region having a first reflection factor and a second film-thickness region having a second reflection factor which are predetermined against light is formed on the surface of the non-single- crystal semiconductor layer 3 which has been made smooth. In addition, the surface of the antireflection film 4 is irradiated with light. The non-single-crystal semiconductor layer is melted; after that, it is cooled and transformed into a single crystal to form a second single-crystal semiconductor layer 8. Thereby, a single-crystal silicon layer whose surface shape is smooth can be formed on the insulating layer.

93. 发明专利

JPH03201459A WAFER CARRIER 失效
公开(公告)号：JPH03201459A
公开(公告)日：1991-09-03
申请号：JP34023789
申请日：1989-12-28
申请人： MITSUBISHI ELECTRIC CORP
发明人： TO KAZUHITO , NAKAO SHIN , IPPOSHI TAKASHI
IPC分类号： H01L21/673 , H01L21/68
摘要： PURPOSE:To fix a semiconductor wafer with a hollow cushion at transfer so as to prevent the wafer from oscillating by a method wherein the hollow cushion is provided in a groove provided on a carrier main body, and the cushion is made to expand. CONSTITUTION:When a prescribed pieces of semiconductor wafers are housed in a wafer carrier 10, a pressure adjustment section 5 dedicated plug is inserted into an opening, and then a compressor is made to start operating to send air into a hollow cushion 4 to increase the inner pressure of the cushion 4. By this setup, the hollow cushion 4 is made to expand from the bases of grooves 3a and 3b to fix the peripheral part Wa of a semiconductor wafer W by holding it with its expanded region. Thereafter, an operator or an automatic robot transfers the wafer carrier 10 to a prescribed position. At this time, the semiconductor wafers W are completely held and fixed by the hollow cushion 4, so that the semiconductor wafers W are prevented from oscillating in the grooves 3a and 3b.

94. 发明专利

JPH03142965A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03142965A
公开(公告)日：1991-06-18
申请号：JP28334889
申请日：1989-10-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUGAHARA KAZUYUKI , IPPOSHI TAKASHI
IPC分类号： H01L21/8238 , H01L27/00 , H01L27/092
摘要： PURPOSE:To prevent the characteristics deterioration of a semiconductor element by depositing a semiconductor layer composed of nonmonocrystal on control electrodes, heat-treating said semiconductor layer by using stationary heat flow, and eliminating the semiconductor layer parts corresponding with the control electrodes by etching. CONSTITUTION:A semiconductor layer 30 composed of nonmonocrystal is deposited on control electrodes 5, 20; the layer 30 is heat-treated by stationary heat flow; difference is generated between the grain diameter of semiconductor layers 32, 34 on the control electrodes 5, 20 and the grain diameter of semicon ductor layers 31, 33, 35 on the parts other than the control electrodes. Since the smaller the crystal grain diameter is, the larger the etching rate is, the semiconductor layers 32, 34 with small grain diameter on the control electrodes 5, 20 are accurately eliminated, by performing etching for a specified period after heat treatment. Hence conducting layers 2, 3 are accurately formed without deviating from previously determined forming positions. Thereby the characteristics deterioration of a semiconductor element formed on the control electrodes can be prevented.

95. 发明专利

JPH0355830A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0355830A
公开(公告)日：1991-03-11
申请号：JP19188889
申请日：1989-07-25
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAMAGUCHI YASUO , NISHIMURA TADASHI , INOUE YASUAKI , SUGAHARA KAZUYUKI , IPPOSHI TAKASHI
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205
摘要： PURPOSE:To obtain silicified contact structure having excellent electrical connection by forming a wiring layer having two-layer structure composed of a thin polysilicon layer and a metallic silicide layer shaped onto the polysilicon layer onto a through-hole formed to an insulating layer on a semiconductor substrate. CONSTITUTION:An insulating layer 2 shaped onto a semiconductor substrate 1, a through-hole 3 formed to the insulating layer 2 so that the semiconductor substrate 1 is exposed, a thin polysilicon layer 4 shaped onto at least the through-hole 3, and a metallic layer 6 formed onto the thin polysilicon layer 4 are shaped. The insulating layer 2 is formed onto the semiconductor substrate 1, the through-hole 3 is shaped onto the insulating layer 2 so that the semiconductor substrate 1 is exposed, and the polysilicon layer 4 is formed onto at least the through-hole 3. A metallic layer 5 is shaped onto the polysilicon layer 4, the metallic layer 5 and polysilicon are reacted, two-layer structure in which the metallic silicide layer 6 is formed onto the unreacted thin polysilicon layer 4 left, and the unreacted metallic layer 5 on the insulating layer 2 is removed selectively.

96. 发明专利

JP2003092360A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003092360A
公开(公告)日：2003-03-28
申请号：JP2001284866
申请日：2001-09-19
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAEDA SHIGENOBU , IPPOSHI TAKASHI , HIRANO YUICHI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L27/08 , H01L27/092 , H01L29/786 , H01L29/94
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device consisting of capacitance of a high Q factor. SOLUTION: In an SOI substrate consisting of a supporting board 165, an embedded oxide film 166, and an SOI layer 171, element isolation (partial isolation) structure is obtained by selectively forming isolating oxide films 167 (167a-167c), leaving a part of the SOI layer 171 as a P -well region 169, at the upper layer part of the SOI layer 171, and a junction variable capacitor C23, which has a PN junction face between the P -well region 169 under the isolating oxide film 167b and the N diffusion region 168, is obtained by forming the N diffusion region 168 in the SOI layer 171 between the isolating oxide films 167a and 167b, and forming a p diffusion region 170 in the SOI layer 171 between the isolating oxide films 167b and 167c.

97. 发明专利

JP2002208705A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002208705A
公开(公告)日：2002-07-26
申请号：JP2001001418
申请日：2001-01-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAEDA SHIGENOBU , IWAMATSU TOSHIAKI , IPPOSHI TAKASHI
IPC分类号： H01L27/08 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is provided with an SOI structure for fixing a part partially separated to reduce a body resistance, and to provide its manufacturing method. SOLUTION: When a source drain area of an NMOS transistor is formed, an N type impurity is hard to be injected into a well area 11 under an extended area 41a in the direction of gate because of the extended area 41a in the direction of gate of an N+ block area in an N+ block resist 51. Thus, the well area 11, as a high resistance formation area that the N type impurity may be injected in the extension line in the lengthwise direction of a gate electrode 9, is made a high resistance formation area A2 that is narrower than the conventional high resistance formation area A1.

98. 发明专利

JP2000173976A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000173976A
公开(公告)日：2000-06-23
申请号：JP34263998
申请日：1998-12-02
申请人： MITSUBISHI ELECTRIC CORP
发明人： IPPOSHI TAKASHI , IWAMATSU TOSHIAKI
IPC分类号： H01L21/306 , H01L21/3065 , H01L21/336 , H01L21/762 , H01L27/08 , H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To prevent a crystal defect from being generated in an SOI layer by a method wherein the SOI layer on an SOI substrate is isotropically etched with an NH3-H2O2-H2O solution to form the SOI layer into a thin film having a prescribed thickness, and a semiconductor device is formed on the thinned SOI layer. SOLUTION: In an SOI(single crystal silicon) substrate 10, a buried oxide film 2 and an SOI layer 3 are laminated on the main surface of a silicon substrate 1. Such a SOI substrate 10 is dipped in an etching tank filled with NH3-H2 O2-H2O solution of a ratio of components set to 1:1:5 to perform an isotropic etching on the substrate 10 using the solution as an etchant, silicon atoms are removed in order from the surface of the layer 3, which is formed into a thin film of a prescribed thickness. A semiconductor device is formed on the thinned SOI layer 3. Thereby, crystal defects can be prevented from being generated in the layer 3 due to excessive silicon atoms.

99. 发明专利

JP2000031489A MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000031489A
公开(公告)日：2000-01-28
申请号：JP19280198
申请日：1998-07-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： MIYAMOTO SHOICHI , IPPOSHI TAKASHI
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L27/12 , H01L29/49 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an SOIMOS transistor, whereby the insulation breakdown of a gate oxide film at the end edge of an SOI(Si-on- insulator) layer in the SOIMOS transistor with elements isolated by trenches is prevented and a parasitic MOS transistor is prevented from being formed at the end edge of the SOI layer below gate electrodes. SOLUTION: After removing a nitride film by phosphoric acid at about 160 deg.C, a polysilicon film is removed by isotropic dry etching, to result in a shape such that an underlying oxide film 4 and side wall oxide film 7 are surrounded with a deposition oxide film 8 and left, and the underlying oxide film 4, a sidewall oxide film 7 and deposition oxide film 8 are removed by hydrofluoric acid at the same time.

100. 发明专利

JPH10242468A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH10242468A
公开(公告)日：1998-09-11
申请号：JP4225097
申请日：1997-02-26
申请人： MITSUBISHI ELECTRIC CORP
发明人： IWAMATSU TOSHIAKI , IPPOSHI TAKASHI
IPC分类号： H01L21/265 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To prevent an impurity by introducing nitrogen so that an area near an interface between a first semiconductor region and a buried oxide film has a first peak that projects with a first concentration and an area near an interface between the first semiconductor region and a gate oxide has a second peak part that projects with a second concentration. SOLUTION: A resist 22b is formed on a PMOS region PR and an impurity ion is implanted into an NMOS region NR with it as a mask, thus causing an SOI layer 3 of the NMOS region NR to become a channel dope layer (a first semiconductor region). Then, with the resist 22b as a mask, nitrogen N is ion-implanted into the NMOS region NR. The resist 22c is formed on the NMOS region NR and an impurity ion is implanted into the PMOS region PR with it as a mask. Then, with the resist 22c as a mask, nitrogen is ion- implanted into the PMOS region PR. Nitrogen is trapped by a crystal defect instead of an impurity, thus preventing an active impurity from decreasing.

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