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91. 发明申请

US20080261071A1 Preserving Solderability and Inhibiting Whisker Growth in Tin Surfaces of Electronic Components 审中-公开
标题翻译：保持电子元件锡表面的可焊性和抑制晶须生长
公开(公告)号：US20080261071A1
公开(公告)日：2008-10-23
申请号：US10597374
申请日：2005-01-21
申请人： Chen Xu , Yun Zhang , Chonglun Fan , Oscar Khaselev , Joseph A. Abys , Eric Walch , Marlies Kleinfeld , Hans Ullrich Eckert
发明人： Chen Xu , Yun Zhang , Chonglun Fan , Oscar Khaselev , Joseph A. Abys , Eric Walch , Marlies Kleinfeld , Hans Ullrich Eckert
IPC分类号： B32B15/01 , C25D5/12
CPC分类号： H01L23/49582 , C25D5/12 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2924/00014 , H01L2924/01327 , H01L2924/15747 , H01L2924/19041 , H01R4/02 , H01R13/03 , H05K3/3426 , H05K2201/10909 , Y02P70/613 , Y10T428/12722 , H01L2224/45099 , H01L2924/00
摘要： A method for reducing whisker formation and preserving solderability in tin coatings over metal features of electronic components. The tin coating has internal tensile stress and is between about 0.5 m and about 4.0 m in thickness. There is a nickel-based layer under the tin coating.
摘要翻译：一种减少电子部件的金属特征的方法，用于减少锡涂层中的晶须形成和保持锡涂层的可焊性。锡涂层具有内部拉伸应力，厚度在约0.5μm至约4.0μm之间。在锡涂层下面有一个镍基层。

92. 发明授权

US07369974B2 Polynomial generation method for circuit modeling 有权
标题翻译：电路建模的多项式生成方法
公开(公告)号：US07369974B2
公开(公告)日：2008-05-06
申请号：US11217577
申请日：2005-08-31
申请人： Yifeng Yang , Yun Zhang
发明人： Yifeng Yang , Yun Zhang
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/08
摘要： A method for determining polynomials to model circuit delay includes the step of determining one or more error areas in a characteristic map that exceed an error margin. Next, a current domain count is set to zero and selecting one error area of the one or more error areas is selected. A patch region that will contain the error area determined the patch region is then curve fitted and the current domain count is increased by one. The steps of repeating steps of selecting an error area, determine a patch, curve fitting within the patch, and increasing the domain count by one are repeated until there are no error area within the patch region. Then a previous domain region having the largest domain count and at last one error area is curve fitted without using data points in any of the domain regions greater than the previous domain region if the previous domain region contains at least one error area, repeating steps of selecting an error area, determine a patch, curve fitting within the patch, and increasing the domain count by one. Then, a domain region having at least one error area is selected as the previous domain region. The steps of curve fitting a previous domain level having at least one error area is repeated for all domain regions less than the previous domain region that has at least one error areas, until all error areas are removed from all domain regions. Additionally, the method can include using a nth order polynomial for curve fitting and associating the polynomial with the current domain region.
摘要翻译：用于确定多项式以建模电路延迟的方法包括确定特征图中超过误差容限的一个或多个误差区域的步骤。接下来，将当前域计数设置为零，并且选择一个或多个错误区域的一个错误区域。将包含确定补丁区域的错误区域的补丁区域然后进行曲线拟合，并将当前域计数增加1。重复选择错误区域，确定补丁，补丁内的曲线拟合以及将域数增加1的步骤的重复步骤，直到补丁区域内没有错误区域。然后，如果先前的域区域包含至少一个错误区域，则具有最大域计数和最后一个错误区域的先前域区域被曲线拟合，而不使用大于先前域区域的任何域区域中的数据点，重复步骤选择错误区域，确定补丁中的补丁，曲线拟合，并将域计数增加1。然后，选择具有至少一个错误区域的域区域作为先前的域区域。对于具有至少一个误差区域的先前域区域的所有域区域重复对具有至少一个误差区域的先前域级别的曲线拟合步骤，直到从所有域区域移除所有错误区域。此外，该方法可以包括使用用于曲线拟合的第n阶多项式并将多项式与当前域区域相关联。

93. 发明申请

US20070037377A1 TIN-SILVER SOLDER BUMPING IN ELECTRONICS MANUFACTURE 有权
标题翻译：锡银焊接电子制造
公开(公告)号：US20070037377A1
公开(公告)日：2007-02-15
申请号：US11463355
申请日：2006-08-09
申请人： Thomas Richardson , Marlies Kleinfeld , Christian Rietmann , Igor Zavarine , Ortrud Steinius , Yun Zhang , Joseph Abys
发明人： Thomas Richardson , Marlies Kleinfeld , Christian Rietmann , Igor Zavarine , Ortrud Steinius , Yun Zhang , Joseph Abys
IPC分类号： H01L21/44
CPC分类号： H01L21/2885 , C25D3/60 , C25D21/18 , H01L24/11 , H01L24/12 , H01L2224/11462 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01047 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014
摘要： A process for forming a solder bump on an under bump metal structure in the manufacture of a microelectronic device comprising exposing the under bump metal structure to an electrolytic bath comprising a source of Sn2+ ions, a source of Ag+ ions, a thiourea compound and/or a quaternary ammonium surfactant; and supplying an external source of electrons to the electrolytic bath to deposit a Sn—Ag alloy onto the under bump metal structure.
摘要翻译：一种用于在微电子器件的制造中在下凸块金属结构上形成焊料凸块的工艺，包括将凸块下金属结构暴露于包含Sn 2+离子源的电解槽， AgO +离子，硫脲化合物和/或季铵表面活性剂; 并向电解槽提供外部电子源，以将Sn-Ag合金沉积到下凸块金属结构上。

94. 发明授权

US06730209B2 Solder electroplating bath including brighteners having reduced volatility 有权
标题翻译：焊接电镀浴，包括挥发性降低的增白剂
公开(公告)号：US06730209B2
公开(公告)日：2004-05-04
申请号：US10081326
申请日：2002-02-22
申请人： Joseph A. Abys , Frank Stanley Humiec , Kenneth J. Murski , Yun Zhang
发明人： Joseph A. Abys , Frank Stanley Humiec , Kenneth J. Murski , Yun Zhang
IPC分类号： C25D360
CPC分类号： C25D3/32 , C25D3/36 , C25D3/60 , H05K3/3473
摘要： In accordance with the invention, the volatility of a solder plating bath with volatile brighteners such as aldehydes has its volatility reduced by the addition of diols to the bath. The diols are advantageously 1,3 propanediol or 1,2 propanediol and are accompanied by lower molecular weight alcohols. In a preferred embodiment, a diol along with low alcohol is added to a bath comprising sulfonic acid, surfactant, grain refiner and brightening agents comprising an aromatic aldehyde and a carboxylic acid.
摘要翻译：根据本发明，具有挥发性增白剂如醛的焊料镀浴的挥发性通过向浴中加入二醇来降低挥发性。二醇有利地为1,3-丙二醇或1,2-丙二醇，并且伴随有较低分子量的醇。在优选的实施方案中，将二醇与低级醇一起加入到包含磺酸，表面活性剂，晶粒细化剂和包含芳族醛和羧酸的增白剂的浴中。

95. 发明授权

US5750017A Tin electroplating process 失效
标题翻译：锡电镀工艺
公开(公告)号：US5750017A
公开(公告)日：1998-05-12
申请号：US697150
申请日：1996-08-21
申请人： Yun Zhang
发明人： Yun Zhang
IPC分类号： C25D3/32 , C25D3/60 , C25D5/18 , C25D7/00
CPC分类号： C25D5/18 , C25D3/32 , C25D3/60
摘要： A process for plating tin or tin alloy onto metal substrates is described. In the process, a metal substrate is placed in an electroplating bath that contains a stannous sulfate and an organic compound additive in which the organic compound has a heterocyclic moiety in an aqueous solution of sulfonic acid. The bath is then subjected to pulse plating conditions that plate a layer of tin or tin alloy onto the metal substrate wherein the tin in the tin layer has a grain size of about 2 .mu.m to about 8 .mu.m. During pulse plating, a current density of about 65 ASF to about 250 ASF is applied to the electroplating bath in a pulsed manner, i.e. the current is cycled on and off during plating. The duty cycle of the pulse is about twenty-five percent to about thirty percent. The duration of the on pulse during the cycle is about 50 .mu.s to about 500 .mu.s.
摘要翻译：描述了将锡或锡合金镀在金属基底上的方法。在该方法中，将金属基材放置在含有硫酸亚锡和有机化合物添加剂的电镀浴中，其中有机化合物在磺酸的水溶液中具有杂环部分。然后对该浴进行脉冲电镀条件，其将锡或锡合金层铺在金属基底上，其中锡层中的锡具有约2μm至约8μm的晶粒尺寸。在脉冲电镀期间，脉冲方式将电流密度约为65 ASF至约250 ASF施加到电镀槽，即在电镀过程中电流循环。脉搏的占空比约为百分之二十五至百分之三十。循环期间的通脉冲持续时间约为50μs至约500μs。

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