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91. 发明申请

US20110075493A1 NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE WORDLINE VOLTAGE OF THE SAME 有权
标题翻译：非易失性存储器件和控制其相位电压的方法
公开(公告)号：US20110075493A1
公开(公告)日：2011-03-31
申请号：US12895350
申请日：2010-09-30
申请人： Min-Su Kim , Hyung-Gon Kim
发明人： Min-Su Kim , Hyung-Gon Kim
IPC分类号： G11C7/22
CPC分类号： G11C16/30
摘要： A nonvolatile memory device includes an array of memory cells arranged in rows and columns, the array of memory cells having wordlines associated therewith. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages at the determined levels. Related methods are also provided.
摘要翻译：非易失性存储器件包括排列成行和列的存储器单元阵列，存储器单元阵列具有与之相关联的字线。字线电压控制器确定要提供给各个字线的字线电压的电平，并且字线电压发生器以所确定的电平产生字线电压。还提供了相关方法。

92. 发明申请

US20100315144A1 Flip-Flop Circuits and System Including the Same 有权
标题翻译：触发电路和包括它的系统
公开(公告)号：US20100315144A1
公开(公告)日：2010-12-16
申请号：US12797852
申请日：2010-06-10
申请人： Hyoung-Wook Lee , Min-Su Kim
发明人： Hyoung-Wook Lee , Min-Su Kim
IPC分类号： H03K3/356 , H03K3/00
CPC分类号： H03K3/356191
摘要： Flip-flop circuits including a dynamic input unit and a control clock generator are provided. The dynamic input unit precharges an evaluation node to a power supply voltage in a first phase of a clock signal, selectively discharges the evaluation node based on input data in a second phase of the clock signal, and compensates for voltage drop of the evaluation node in response to a first control clock signal. The control clock generator generates the first control clock signal and a second control clock signal based on at least the clock signal.
摘要翻译：提供了包括动态输入单元和控制时钟发生器的触发电路。动态输入单元在时钟信号的第一阶段中将评估节点预充电到电源电压，基于时钟信号的第二相位中的输入数据选择性地放电评估节点，并且补偿评估节点的电压降响应于第一控制时钟信号。控制时钟发生器至少基于时钟信号产生第一控制时钟信号和第二控制时钟信号。

93. 发明授权

US07852698B2 Voltage supply device and nonvolatile memory device having the same 有权
标题翻译：电压供应装置和具有该电压装置的非易失性存储装置
公开(公告)号：US07852698B2
公开(公告)日：2010-12-14
申请号：US12287184
申请日：2008-10-07
申请人： Min-Su Kim , Byoung-Ho Kim , Sung-Woo Park , Weon-Ho Park
发明人： Min-Su Kim , Byoung-Ho Kim , Sung-Woo Park , Weon-Ho Park
IPC分类号： G11C7/00
CPC分类号： H02M3/073 , G11C16/30 , H02M2001/0045
摘要： A voltage supply device comprises: a charge pump configured to boost a power voltage and to supply the boosted power voltage to a output line; and a voltage control circuit configured to maintain a voltage level of the output line at a target voltage level; wherein the voltage control circuit comprises a reach-through element including a first region and a second region provided in a well, the reach-through element configured to control the voltage level of the output line, using a reach-through function between the first region and the second region.
摘要翻译：电压供给装置包括：电荷泵，被配置为升高电源电压并将升压的电源电压提供给输出线; 以及电压控制电路，被配置为将所述输出线的电压电平保持在目标电压电平; 其中所述电压控制电路包括直通元件，其包括设置在阱中的第一区域和第二区域，所述贯穿元件被配置为使用所述第一区域之间的到达功能来控制所述输出线路的电压电平和第二个地区。

94. 发明授权

US07706653B2 Optical waveguide device 有权
标题翻译：光波导器件
公开(公告)号：US07706653B2
公开(公告)日：2010-04-27
申请号：US11857262
申请日：2007-09-18
申请人： Suntak Park , Seok Ho Song , Hyong Sik Won , Myung-Hyun Lee , Jung Jin Ju , Min-Su Kim , Jin Tae Kim , Seung Koo Park
发明人： Suntak Park , Seok Ho Song , Hyong Sik Won , Myung-Hyun Lee , Jung Jin Ju , Min-Su Kim , Jin Tae Kim , Seung Koo Park
IPC分类号： G02B6/10
CPC分类号： G02B6/1226 , B82Y20/00
摘要： Provided is an optical waveguide device including: a core having a stacked structure of at least three layers in which first thin films having a finite width and thickness and formed of a material having a relatively high electric conductivity and a second thin film having the same width as the first thin films and formed of a material having a lower conductivity than the material forming the first thin films are stacked in sequence, the first thin films being disposed in a first layer and an uppermost layer and adjacent to each other for interaction of surface plasmons; and a clad disposed around the core and formed of a material having a lower conductivity than the material forming the first thin films and a higher refractive index than the material forming the second thin film. The thin metal films of at least two layers having a high electric conductivity in the optical waveguide device can generate a combined surface plasmon mode and propagate the generated surface plasmon mode in the length direction of the thin metal films. Thus, a propagated signal suffers from a smaller propagation loss than a surface plasmon mode supported by a single thin film.
摘要翻译：本发明提供一种光波导装置，其特征在于，包括：具有层叠结构的至少3层的芯，其中具有有限宽度和厚度的第一薄膜由具有较高导电性的材料形成，并且具有相同宽度的第二薄膜因为第一薄膜并且由具有比形成第一薄膜的材料的导电性低的材料形成的材料依次层叠，所以第一薄膜被布置在第一层和最上层中并且彼此相邻以相互作用等离子体激元以及围绕芯部设置的包层，其由比形成第一薄膜的材料低的导电性材料形成，并且比形成第二薄膜的材料具有更高的折射率。在光波导器件中具有高电导率的至少两层的金属薄膜可以产生组合的表面等离子体激元模式，并且在薄金属薄膜的长度方向上传播产生的表面等离子体激元模式。因此，传播信号比由单个薄膜支持的表面等离子体模式传播损耗更小。

95. 发明授权

US07528630B2 High speed flip-flop 失效
标题翻译：高速触发器
公开(公告)号：US07528630B2
公开(公告)日：2009-05-05
申请号：US11970629
申请日：2008-01-08
申请人： Min-Su Kim , Bai-Sun Kong
发明人： Min-Su Kim , Bai-Sun Kong
IPC分类号： H03K19/00
CPC分类号： H03K3/356121
摘要： A flip-flop circuit includes a precharging circuit which precharges a first circuit node in response to a first pulse signal and an estimation circuit that receives an input signal and a second pulse signal. The estimation circuit discharges the voltage from the first node in response to the input signal on activation of the second pulse signal. The first pulse signal is synchronized to a clock signal and the second pulse signal is delayed from the first pulse signal.
摘要翻译：触发器电路包括：预充电电路，其响应于第一脉冲信号对第一电路节点进行预充电;以及估计电路，其接收输入信号和第二脉冲信号。在激活第二脉冲信号时，估计电路响应于输入信号从第一节点放电电压。第一脉冲信号与时钟信号同步，第二脉冲信号从第一脉冲信号延迟。

96. 发明授权

US07504871B2 Flip-flops and electronic digital circuits including the same 有权
标题翻译：触发器和包括其的电子数字电路
公开(公告)号：US07504871B2
公开(公告)日：2009-03-17
申请号：US11819388
申请日：2007-06-27
申请人： Min-Su Kim , Bai-Sun Kong
发明人： Min-Su Kim , Bai-Sun Kong
IPC分类号： H03K3/00
CPC分类号： H03K3/356121 , H03K3/356147 , H03K3/356191
摘要： A flip-flop includes a first circuit receiving a clock signal and the first signal and transitioning the first and second output signals to a first level when the clock signal goes to an active level, and a second circuit transitioning the first signal to the first level after the first and second output signals go to the first level. The first circuit transfers first and second input signals to the first and second output terminals from first and second input terminals when the clock signal is at the active level and the first signal is at the first level.
摘要翻译：触发器包括接收时钟信号和第一信号的第一电路，并且当时钟信号进入有效电平时，将第一和第二输出信号转换到第一电平，第二电路将第一信号转换到第一电平在第一和第二输出信号进入第一级之后。当时钟信号处于有效电平并且第一信号处于第一电平时，第一电路将第一和第二输入信号从第一和第二输入端传送到第一和第二输出端。

97. 发明申请

US20080226222A1 OPTO-ELECTRIC BUS MODULE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：光电总线模块及其制造方法
公开(公告)号：US20080226222A1
公开(公告)日：2008-09-18
申请号：US12049261
申请日：2008-03-14
申请人： Jin Tae Kim , Suntak Park , Jung Jin Ju , Seung Koo Park , Min-Su Kim , Myung Hyun Lee
发明人： Jin Tae Kim , Suntak Park , Jung Jin Ju , Seung Koo Park , Min-Su Kim , Myung Hyun Lee
IPC分类号： G02B6/12 , B05D5/06
CPC分类号： G02B6/423 , G02B6/4214 , G02B6/43
摘要： Provided are an opto-electric bus module and a method of manufacturing the opto-electric bus module. The opto-electric bus module includes an opto-electric interconnection unit where a concave-shaped micro structure is formed on a lower surface of a polymer structure and an optical bench where a convex-shaped micro structure is formed in a position corresponding to the concave-shaped micro structure, at least one second electric interconnection for electric connection with a semiconductor chip is formed, and the semiconductor chip and an opto-electric device can be mounted. Thus, automatic, efficient, high-speed, and high-integration optical communication and electric communication between multi-chips can be completed at the same time by using the opto-bus module which provides low-speed electric communication while manually maintaining solid optical coupling.
摘要翻译：提供了一种光电总线模块和一种制造光电总线模块的方法。光电总线模块包括光电互连单元，其中在聚合物结构的下表面上形成凹形微结构，在其上形成凸形微结构在与凹部对应的位置形成微型结构，形成至少一个用于与半导体芯片电连接的第二电互连，并且可以安装半导体芯片和光电装置。因此，可以通过使用提供低速电气通信的光总线模块同时完成多芯片之间的自动，高效，高集成度的光通信和电通信，同时手动保持固体光耦合。

98. 发明授权

US07358786B2 Control signal generator, latch circuit, flip flop and method for controlling operations of the flip-flop 有权
标题翻译：控制信号发生器，锁存电路，触发器和用于控制触发器操作的方法
公开(公告)号：US07358786B2
公开(公告)日：2008-04-15
申请号：US11128294
申请日：2005-05-13
申请人： Min-Su Kim
发明人： Min-Su Kim
IPC分类号： H03K3/356
CPC分类号： G01R31/318575 , G01R31/318552 , H03K3/0375
摘要： A control signal generator, latch circuit, flip-flop and method for controlling operations in the flip-flop may be configured so as to efficiently perform latching and scanning operations in the flip-flop. The control signal generator may generate at least two pulses based on a scan enable signal being received in a first state and on a received clock signal, and may generate at least two internal clock signals based on the received clock signal, and based on the scan enable signal being received in a second state. The latch circuit may latch a received input signal based on the at least two pulses and may latch a received scan input signal based on the at least two internal clock signals.
摘要翻译：可以配置用于控制触发器中的操作的控制信号发生器，锁存电路，触发器和方法，以有效地执行触发器中的锁存和扫描操作。控制信号发生器可以基于在第一状态和接收的时钟信号中接收到的扫描使能信号来生成至少两个脉冲，并且可以基于接收到的时钟信号，并且基于扫描来生成至少两个内部时钟信号使能信号在第二状态下被接收。锁存电路可以基于至少两个脉冲来锁存接收到的输入信号，并且可以基于至少两个内部时钟信号来锁存接收到的扫描输入信号。

99. 发明申请

US20070080734A1 Pulse-based flip-flop 审中-公开
公开(公告)号：US20070080734A1
公开(公告)日：2007-04-12
申请号：US11635015
申请日：2006-12-07
申请人： Min-Su Kim
发明人： Min-Su Kim
IPC分类号： H03K3/00
CPC分类号： H03K5/151 , H03K3/037 , H03K5/135 , H03K5/1534
摘要： A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

100. 发明申请

US20060097754A1 Gated clock logic circuit 有权
标题翻译：门控时钟逻辑电路
公开(公告)号：US20060097754A1
公开(公告)日：2006-05-11
申请号：US11266659
申请日：2005-11-02
申请人： Min-Su Kim
发明人： Min-Su Kim
IPC分类号： H03K19/096
CPC分类号： G06F1/04 , G06F1/3237 , H03K3/012 , H03K3/356121 , H03K5/135 , Y02D10/128
摘要： A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and a control signal.
摘要翻译：门控时钟逻辑电路包括脉冲发生器和预充电锁存器。脉冲发生器响应于时钟信号产生脉冲信号，并且预充电锁存器响应于时钟信号，脉冲信号和控制信号产生门控时钟信号。

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