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91. 发明申请

US20080127035A1 WATCHPOINTS ON TRANSACTIONAL VARIABLES 有权
标题翻译：对交易变量的看法
公开(公告)号：US20080127035A1
公开(公告)日：2008-05-29
申请号：US11552903
申请日：2006-10-25
申请人： Yosef Lev , Mark S. Moir
发明人： Yosef Lev , Mark S. Moir
IPC分类号： G06F9/44
CPC分类号： G06F11/362
摘要： Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. However, various features and capabilities that would be desirable for debugging programs executed using transactional memory are absent from conventional debuggers. Because transactional memory implementations provide the “illusion” of multiple memory locations changing value atomically, while in fact they do not, there can be significant challenges involved with integrating debuggers with such programs to provide the user with a coherent view of program execution. We describe use of transactional memory access tracking mechanism for implementations of watchpoints on memory locations that correspond to transactional variables.
摘要翻译：事务性规划将大大简化正确，可扩展和高效并发程序的开发和维护。最近出现了使用在硬件，软件和两者的混合中实现的事务性存储来支持事务性编程的设计。然而，常规调试器中不存在用于使用事务性存储器执行的调试程序所需的各种功能和功能。因为事务性存储器实现提供了多个存储器位置以原子方式改变值的“错觉”，而实际上它们并不存在，因此将调试器与这些程序集成可能会带来重大挑战，从而向用户提供程序执行的一致的视图。我们描述了使用事务性内存访问跟踪机制来实现对应于事务变量的内存位置上的观察点。

92. 发明授权

US07299242B2 Single-word lock-free reference counting 有权
标题翻译：单字无锁引用计数
公开(公告)号：US07299242B2
公开(公告)日：2007-11-20
申请号：US10340150
申请日：2003-01-10
申请人： Mark S. Moir , Victor Luchangco , Maurice Herlihy
发明人： Mark S. Moir , Victor Luchangco , Maurice Herlihy
IPC分类号： G06F9/46 , G06F9/44 , G06F12/00
CPC分类号： G06F9/52 , Y10S707/99944 , Y10S707/99947 , Y10S707/99953
摘要： Solutions to a value recycling problem that we define herein facilitate implementations of computer programs that may execute as multithreaded computations in multiprocessor computers, as well as implementations of related shared data structures. Some exploitations of the techniques described herein allow non-blocking, shared data structures to be implemented using standard dynamic allocation mechanisms (such as malloc and free). A class of general solutions to value recycling is described in the context of an illustration we call the Repeat Offender Problem (ROP), including illustrative Application Program Interfaces (APIs) defined in terms of the ROP terminology. Furthermore, specific solutions, implementations and algorithm, including a Pass-The-Buck (PTB) implementation are also described. Solutions to the proposed value recycling problem have a variety of uses. For example, a single-word lock-free reference counting (SLFRC) technique may build on any of a variety of value recycling solutions to transform, in a straight-forward manner, many lock-free data structure implementations that assume garbage collection (i.e., which do not explicitly free memory) into dynamic-sized data structures.
摘要翻译：我们在这里定义的价值回收问题的解决方案便于在多处理器计算机中作为多线程计算执行的计算机程序的实现，以及相关共享数据结构的实现。本文描述的技术的一些利用允许使用标准动态分配机制（诸如malloc和free）来实现非阻塞的共享数据结构。在我们称为重复违规问题（ROP）的例证的上下文中描述了一类价值回收的一般解决方案，包括根据ROP术语定义的说明性应用程序接口（API）。此外，还描述了包括通过降压（PTB）实现的具体解决方案，实现和算法。提出的价值回收问题的解决方案有各种用途。例如，单字无锁引用计数（SLFRC）技术可以建立在各种价值回收解决方案中的任何一种上，以直接方式转换许多无锁数据结构实现，这些实现假定垃圾收集（即，不明确地释放内存）到动态大小的数据结构中。

93. 发明授权

US07206903B1 Method and apparatus for releasing memory locations during transactional execution 有权
标题翻译：在事务执行期间释放内存位置的方法和装置
公开(公告)号：US07206903B1
公开(公告)日：2007-04-17
申请号：US10895519
申请日：2004-07-20
申请人： Mark S. Moir , Maurice P. Herlihy , Quinn A. Jacobson , Shailender Chaudhry , Marc Tremblay
发明人： Mark S. Moir , Maurice P. Herlihy , Quinn A. Jacobson , Shailender Chaudhry , Marc Tremblay
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F9/30087 , G06F9/3834 , G06F9/3859
摘要： One embodiment of the present invention provides a system for releasing a memory location from transactional program execution. The system operates by executing a sequence of instructions during transactional program execution, wherein memory locations involved in the transactional program execution are monitored to detect interfering accesses from other threads, and wherein changes made during transactional execution are not committed until transactional execution completes without encountering an interfering data access from another thread. Upon encountering a release instruction for a memory location during the transactional program execution, the system modifies state information within the processor to release the memory location from monitoring. The system also executes a commit-and-start-new-transaction instruction, wherein the commit-and-start-new-transaction instruction atomically commits the transaction's stores, thereby removing them from the transaction's write set while the transaction's read set remains unaffected.
摘要翻译：本发明的一个实施例提供了一种用于将存储器位置从事务程序执行释放的系统。该系统通过在事务性程序执行期间执行指令序列来操作，其中监视涉及事务性程序执行的存储器位置以检测来自其他线程的干扰访问，并且其中在事务执行期间进行的改变不会被提交直到事务执行完成而不遇到干扰来自另一个线程的数据访问。在事务性程序执行期间遇到存储器位置的释放指令时，系统修改处理器内的状态信息以从监视释放存储器位置。该系统还执行commit-and-start-new-transaction指令，其中commit-and-start-new-transaction指令以原子方式提交事务的存储，从而在事务的读取集保持不受影响的情况下将其从事务的写入集中移除。

94. 发明授权

US07171537B1 Non-blocking growable arrays 有权
标题翻译：非阻塞可生长阵列
公开(公告)号：US07171537B1
公开(公告)日：2007-01-30
申请号：US10866570
申请日：2004-06-11
申请人： Mark S. Moir , Simon Doherty
发明人： Mark S. Moir , Simon Doherty
IPC分类号： G06F12/00
CPC分类号： G06F12/0646
摘要： A computer system stores a dynamically sized array as a base array that contains references to subarrays in which the (composite) array's data elements reside. Each of the base-array elements that thus refers to a respective subarray is associated with a respective subarray size. Each base-array index is thereby at least implicitly associated with a cumulative base value equal to the sum of all preceding base indexes' associated subarray sizes. In response to a request for access to the element associated with a given (composite-array) index, the array-access system identifies the base index associated with the highest cumulative base value not greater than the composite-array index and performs the access to the subarray identified by the element associated with that base index. Composite-array expansion can be performed in a multi-threaded environment without locking, simply by employing a compare-and-swap or similar atomic operation.
摘要翻译：计算机系统将动态大小的数组存储为基数组，其中包含对（复合）数组元素所在的子阵列的引用。因此，引用相应子阵列的每个基数组元素与相应的子阵列大小相关联。因此，每个基数组索引至少隐含地与等于所有先前的基本索引的相关子阵列大小的总和的累积基值相关联。响应于访问与给定（复合数组）索引相关联的元素的请求，阵列访问系统识别与不大于复合数组索引的最高累积基值相关联的基本索引，并执行对由与该基础索引相关联的元素识别的子阵列。复合阵列扩展可以在没有锁定的多线程环境中执行，简单地通过采用比较和交换或类似的原子操作。

95. 发明授权

US07089374B2 Selectively unmarking load-marked cache lines during transactional program execution 有权
标题翻译：在事务性程序执行期间选择性地取消标记加载标记的高速缓存行
公开(公告)号：US07089374B2
公开(公告)日：2006-08-08
申请号：US10764412
申请日：2004-01-23
申请人： Marc Tremblay , Quinn A. Jacobson , Shailender Chaudhry , Mark S. Moir , Maurice P. Herlihy
发明人： Marc Tremblay , Quinn A. Jacobson , Shailender Chaudhry , Mark S. Moir , Maurice P. Herlihy
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F12/0862
摘要： One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and-start-new-transaction instruction.
摘要翻译：本发明的一个实施例提供了一种系统，其有助于在事务性程序执行期间有选择地取消标记加载标记的高速缓存行，其中在事务执行期间监视负载标记的高速缓存行以检测来自其他线程的干扰访问。在操作期间，系统在事务处理指令块期间遇到释放指令。响应于释放指令，系统修改高速缓存行的状态，这些高速缓存行被特别加载标记以指示它们可以从监视释放，以解决遇到的释放指令。在这样做时，系统可能会导致特别加载标记的高速缓存行变为未标记。在该实施例的变型中，当遇到提交和启动新事务指令时，系统修改加载标记的高速缓存行以考虑正在遇到的提交和启动新事务指令。在这样做时，系统会导致正常加载标记的高速缓存行变为未标记，而其他特别加载标记的高速缓存行可能会通过commit-and-start-new-transaction指令保持加载标记。

96. 发明授权

US07017160B2 Concurrent shared object implemented using a linked-list with amortized node allocation 有权
标题翻译：使用具有摊销节点分配的链接列表实现的并发共享对象
公开(公告)号：US07017160B2
公开(公告)日：2006-03-21
申请号：US09837669
申请日：2001-04-18
申请人： Paul A. Martin , David L. Detlefs , Alexander T. Garthwaite , Guy L. Steele, Jr. , Mark S. Moir
发明人： Paul A. Martin , David L. Detlefs , Alexander T. Garthwaite , Guy L. Steele, Jr. , Mark S. Moir
IPC分类号： G06F9/44 , G06F9/54
CPC分类号： G06F7/785 , G06F9/30032 , G06F9/526 , G06F9/544 , G06F2205/064 , G06F2209/521
摘要： The Hat Trick deque requires only a single DCAS for most pushes and pops. The left and right ends do not interfere with each other until there is one or fewer items in the queue, and then a DCAS adjudicates between competing pops. By choosing a granularity greater than a single node, the user can amortize the costs of adding additional storage over multiple push (and pop) operations that employ the added storage. A suitable removal strategy can provide similar amortization advantages. The technique of leaving spare nodes linked in the structure allows an indefinite number of pushes and pops at a given deque end to proceed without the need to invoke memory allocation or reclamation so long as the difference between the number of pushes and the number of pops remains within given bounds. Both garbage collection dependent and explicit reclamation implementations are described.
摘要翻译：帽子技巧deque只需要一个单一的DCAS大多数按钮和弹出。在队列中有一个或多个项目之前，左右两端不会相互干扰，然后DCAS在竞争弹出之间进行裁决。通过选择大于单个节点的粒度，用户可以通过使用添加的存储的多个推送（和弹出）操作来分摊添加附加存储的成本。合适的清除策略可以提供类似的摊销优势。在结构中链接的备用节点的技术允许在给定的deque端的无限数量的推送和弹出进行，而不需要调用内存分配或回收，只要推送次数和流量数之间的差异保持不变在给定范围内。描述垃圾收集相关和显式回收实现。

97. 发明授权

US09304776B2 System and method for mitigating the impact of branch misprediction when exiting spin loops 有权
标题翻译：退出自旋回路时减轻分支错误预测的影响的系统和方法
公开(公告)号：US09304776B2
公开(公告)日：2016-04-05
申请号：US13362903
申请日：2012-01-31
申请人： David Dice , Mark S. Moir
发明人： David Dice , Mark S. Moir
IPC分类号： G06F9/30 , G06F9/38 , G06F9/32
CPC分类号： G06F9/30058 , G06F9/30079 , G06F9/325 , G06F9/3848
摘要： A computer system may recognize a busy-wait loop in program instructions at compile time and/or may recognize busy-wait looping behavior during execution of program instructions. The system may recognize that an exit condition for a busy-wait loop is specified by a conditional branch type instruction in the program instructions. In response to identifying the loop and the conditional branch type instruction that specifies its exit condition, the system may influence or override a prediction made by a dynamic branch predictor, resulting in a prediction that the exit condition will be met and that the loop will be exited regardless of any observed branch behavior for the conditional branch type instruction. The looping instructions may implement waiting for an inter-thread communication event to occur or for a lock to become available. When the exit condition is met, the loop may be exited without incurring a misprediction delay.
摘要翻译：计算机系统可以在编译时识别程序指令中的忙等待循环和/或可以在程序指令执行期间识别忙等待循环行为。系统可以认识到忙 - 等待循环的退出条件由程序指令中的条件分支类型指令指定。响应于识别循环和指定其退出条件的条件分支类型指令，系统可以影响或覆盖由动态分支预测器做出的预测，导致预测退出条件将被满足，并且循环将退出条件分支类型指令的任何观察到的分支行为。循环指令可以实现等待线程间通信事件发生或锁定变得可用。当满足退出条件时，可以退出循环而不产生误预计延迟。

98. 发明授权

US08417897B2 System and method for providing locale-based optimizations in a transactional memory 有权
标题翻译：用于在事务性存储器中提供基于区域设置的优化的系统和方法
公开(公告)号：US08417897B2
公开(公告)日：2013-04-09
申请号：US12750884
申请日：2010-03-31
申请人： Virendra J. Marathe , Mark S. Moir
发明人： Virendra J. Marathe , Mark S. Moir
IPC分类号： G06F12/00 , G06F9/46
CPC分类号： G06F9/467
摘要： The system and methods described herein may reduce read/write fence latencies and cache pressure related to STM metadata accesses. These techniques may leverage locality information (as reflected by the value of a respective locale guard) associated with each of a plurality of data partitions (locales) in a shared memory to elide various operations in transactional read/write fences when transactions access data in locales owned by their threads. The locale state may be disabled, free, exclusive, or shared. For a given memory access operation of an atomic transaction targeting an object in the shared memory, the system may implement the memory access operation using a contention mediation mechanism selected based on the value of the locale guard associated with the locale in which the target object resides. For example, a traditional read/write fence may be employed in some memory access operations, while other access operations may employ an optimized read/write fence.
摘要翻译：本文描述的系统和方法可以减少与STM元数据访问相关的读/写栅栏延迟和高速缓存压力。这些技术可以利用与共享存储器中的多个数据分区（区域设置）中的每一个相关联的局部性信息（由相应的区域保护的值反映），以便当事务访问区域中的数据时，去除事务读/写栅栏中的各种操作由他们的线程拥有。可以禁用，免费，排他或共享地区状态。对于针对共享存储器中的对象的原子事务的给定存储器访问操作，系统可以使用基于与目标对象所在的区域设置相关联的区域保护的值来选择的争用中介机制来实现存储器访问操作。例如，在一些存储器访问操作中可以采用传统的读/写栅栏，而其他访问操作可以采用优化的读/写栅栏。

99. 发明授权

US08412894B2 Value recycling facility for multithreaded computations 有权
公开(公告)号：US08412894B2
公开(公告)日：2013-04-02
申请号：US13032496
申请日：2011-02-22
申请人： Mark S. Moir , Victor Luchangco , Maurice Herlihy
发明人： Mark S. Moir , Victor Luchangco , Maurice Herlihy
IPC分类号： G06F12/02
CPC分类号： G06F9/52 , Y10S707/955 , Y10S707/99953 , Y10S707/99957
摘要： Solutions to a value recycling problem facilitate implementations of computer programs that may execute as multithreaded computations in multiprocessor computers, as well as implementations of related shared data structures. Some exploitations allow non-blocking, shared data structures to be implemented using standard dynamic allocation mechanisms (such as malloc and free). Some exploitations allow non-blocking, indeed even lock-free or wait-free, implementations of dynamic storage allocation for shared data structures. In some exploitations, our techniques provide a way to manage dynamically allocated memory in a non-blocking manner without depending on garbage collection. While exploitations of solutions to the value recycling problem that we propose include management of dynamic storage allocation wherein values managed and recycled tend to include values that encode pointers, they are not limited thereto. Indeed, the techniques are more generally applicable to management of values in a multithreaded computation. For example, value recycling techniques may be exploited, in some cases, apart from dynamic storage allocation, to allow a multithreaded computation to avoid the classic ABA hazard.

100. 发明申请

US20120310987A1 System and Method for Performing Memory Management Using Hardware Transactions 有权
标题翻译：使用硬件交易执行内存管理的系统和方法
公开(公告)号：US20120310987A1
公开(公告)日：2012-12-06
申请号：US13167606
申请日：2011-06-23
申请人： Aleksandar Dragojevic , Maurice Herlihy , Yosef Lev , Mark S. Moir
发明人： Aleksandar Dragojevic , Maurice Herlihy , Yosef Lev , Mark S. Moir
IPC分类号： G06F17/30
CPC分类号： G06F9/467 , G06F12/0261 , G06F12/0815
摘要： The systems and methods described herein may be used to implement a shared dynamic-sized data structure using hardware transactional memory to simplify and/or improve memory management of the data structure. An application (or thread thereof) may indicate (or register) the intended use of an element of the data structure and may initialize the value of the data structure element. Thereafter, another thread or application may use hardware transactions to access the data structure element while confirming that the data structure element is still part of the dynamic data structure and/or that memory allocated to the data structure element has not been freed. Various indicators may be used determine whether memory allocated to the element element can be freed.
摘要翻译：本文描述的系统和方法可以用于使用硬件事务存储器实现共享的动态大小的数据结构，以简化和/或改善数据结构的存储器管理。应用程序（或其线程）可以指示（或注册）数据结构的元素的预期用途，并且可以初始化数据结构元素的值。此后，另一个线程或应用程序可以使用硬件事务来访问数据结构元素，同时确认数据结构元素仍然是动态数据结构的一部分，和/或分配给数据结构元素的存储器尚未被释放。可以使用各种指示器来确定分配给元素元素的内存是否可以被释放。

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