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91. 发明授权

US08691691B2 TSV pillar as an interconnecting structure 有权
标题翻译： TSV柱作为互连结构
公开(公告)号：US08691691B2
公开(公告)日：2014-04-08
申请号：US13194214
申请日：2011-07-29
申请人： Mukta G. Farooq , Troy L. Graves-Abe , William F. Landers , Kevin S. Petrarca , Richard P. Volant
发明人： Mukta G. Farooq , Troy L. Graves-Abe , William F. Landers , Kevin S. Petrarca , Richard P. Volant
IPC分类号： H01L21/44 , H01L21/311
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/10126 , H01L2224/11009 , H01L2224/1145 , H01L2224/11452 , H01L2224/11602 , H01L2224/11612 , H01L2224/11614 , H01L2224/11616 , H01L2224/13009 , H01L2224/13017 , H01L2224/13022 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13147 , H01L2224/13565 , H01L2224/13583 , H01L2224/13584 , H01L2224/13647 , H01L2224/13655 , H01L2224/13679 , H01L2224/1368 , H01L2224/13681 , H01L2224/13683 , H01L2224/13684 , H01L2224/13687 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/32225 , H01L2224/73203 , H01L2224/81191 , H01L2224/81801 , H01L2224/8385 , H01L2224/9202 , H01L2224/92143 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/351 , H01L2924/3512 , H01L2924/00014 , H01L2924/04953 , H01L2924/0496 , H01L2924/01074 , H01L2924/04941 , H01L2924/053 , H01L2924/014 , H01L2924/00012 , H01L2224/11 , H01L2924/00
摘要： The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.
摘要翻译：本发明包括用于构建具有可用作互连结构的TSV柱的芯片的处理方法和结果的结构的实施例。该过程包括在TSV和衬底之间沉积TSV和衬底之间的双重扩散阻挡层。 TSV然后从衬底的背面露出，使得TSV的至少一部分从衬底突出，并且可以用作用于将芯片连接到另一表面的接触件。所产生的TSV是刚性的，高导电性的，可以放置在紧密连接的接触网格中，并减少CTE失配的影响。

92. 发明授权

US08629553B2 3D integrated circuit device fabrication with precisely controllable substrate removal 有权
标题翻译： 3D集成电路器件制造具有精确可控的衬底去除
公开(公告)号：US08629553B2
公开(公告)日：2014-01-14
申请号：US13398505
申请日：2012-02-16
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
IPC分类号： H01L23/34 , H01L21/30
CPC分类号： H01L27/105 , H01L24/11 , H01L27/0688 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/0557 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599
摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。根据该方法，提供第一有源电路层晶片。第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分。接下来，在P-层的背面上制造布线层。还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

93. 发明申请

US20130307160A1 Via Structure For Three-Dimensional Circuit Integration 有权
标题翻译：通过三维电路集成的结构
公开(公告)号：US20130307160A1
公开(公告)日：2013-11-21
申请号：US13476056
申请日：2012-05-21
申请人： Mukta G. Farooq , Troy L. Graves-Abe , Spyridon Skordas , Kevin R. Winstel
发明人： Mukta G. Farooq , Troy L. Graves-Abe , Spyridon Skordas , Kevin R. Winstel
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L24/09 , H01L21/76898 , H01L23/481 , H01L23/5386 , H01L24/80 , H01L24/82 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L27/0688 , H01L2224/02205 , H01L2224/08145 , H01L2224/0905 , H01L2224/80896 , H01L2224/82031 , H01L2224/82101 , H01L2224/9202 , H01L2224/94 , H01L2225/06544 , H01L2924/0002 , H01L2924/14 , H01L2924/3701 , H01L2924/00 , H01L2224/80
摘要： Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.
摘要翻译：公开了结合三维积分的电路及其制造方法。一个电路包括底层和多个上层。底层包括连接到底层中的功能部件的底部着陆垫。此外，上层堆叠在底层上方。每个上层包括相应的上层板，其连接到各个上层中的各个功能部件。着陆焊盘通过单个导电通孔耦合，并且在底层和上层的堆叠中对准，使得每个着陆焊盘从堆叠中的相邻层中的任何一个着陆焊盘偏移至少一个预定金额。

94. 发明授权

US08563423B2 Fluorine depleted adhesion layer for metal interconnect structure 有权
标题翻译：用于金属互连结构的氟耗尽粘附层
公开(公告)号：US08563423B2
公开(公告)日：2013-10-22
申请号：US13192120
申请日：2011-07-27
申请人： Mukta G. Farooq , Emily R. Kinser
发明人： Mukta G. Farooq , Emily R. Kinser
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05666 , H01L2224/11 , H01L2224/13006 , H01L2924/0002 , H01L2924/00 , H01L2924/00014
摘要： A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.
摘要翻译：在包含氟硅酸盐玻璃（FSG）层的电介质层内形成线槽和通孔。通过从FSG层的暴露表面除去氟的等离子体处理或通过沉积基本上无氟的介电层，在管线槽和通孔内形成氟贫化粘合层。金属沉积在管线槽和通孔腔内以形成金属线和金属通孔。与其中金属线直接接触FSG层的现有技术结构相比，氟贫化粘合层提供对金属线的增强的粘合性。金属与底层电介质层的增强的粘附性对于在金属互连结构上使用无铅C4球的半导体封装提供更高的剥离性。

95. 发明授权

US08563403B1 Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last 有权
标题翻译：首先通过对准通孔/电介质接合的三维集成电路集成，最后通过通孔形成
公开(公告)号：US08563403B1
公开(公告)日：2013-10-22
申请号：US13534067
申请日：2012-06-27
申请人： Mukta G. Farooq , Spyridon Skordas , Richard P. Volant , Kevin R. Winstel
发明人： Mukta G. Farooq , Spyridon Skordas , Richard P. Volant , Kevin R. Winstel
IPC分类号： H01L21/30 , H01L21/46 , H01L21/8238 , H01L21/20
CPC分类号： H01L21/8221 , H01L21/76898 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05078 , H01L2224/05567 , H01L2224/05624 , H01L2224/06181 , H01L2224/08146 , H01L2224/2919 , H01L2224/32145 , H01L2224/80006 , H01L2224/80129 , H01L2224/80896 , H01L2224/83005 , H01L2224/8313 , H01L2224/8385 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2224/83 , H01L2224/80 , H01L2924/00 , H01L2224/05552 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A method includes forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate, a first wiring layer over the alignment via, and a first bonding layer over the first wiring layer; forming a second IC device having a second substrate, a second wiring layer over the second substrate, and a second bonding layer over the second wiring layer; bonding the first bonding layer of first IC device to the second bonding layer of second IC device; thinning a backside of the first IC device so as to expose the alignment via; and using the exposed alignment via to form a deep, through substrate via (TSV) that passes through the first IC device, through a bonding interface between the first IC device and second IC device, and landing on the second wiring layer of the second IC device.
摘要翻译：一种方法包括形成具有第一衬底的第一集成电路（IC）器件，在第一衬底中限定的对准通孔，在对准通孔上方的第一布线层和在第一布线层上的第一接合层; 形成具有第二基板的第二IC器件，在所述第二基板上的第二布线层，以及在所述第二布线层上的第二接合层; 将第一IC器件的第一接合层接合到第二IC器件的第二接合层; 减薄第一IC器件的背面以暴露对准通孔; 以及使用所述暴露的取向通孔，通过所述第一IC器件通过所述第一IC器件和所述第二IC器件之间的接合界面形成穿过所述第一IC器件的深穿通衬底通孔（TSV），并且在所述第二IC器件的第二布线层上着陆设备。

96. 发明申请

US20130122702A1 INTEGRATED VOID FILL FOR THROUGH SILICON VIA 有权
标题翻译：通过硅的集成无孔填充
公开(公告)号：US20130122702A1
公开(公告)日：2013-05-16
申请号：US13555418
申请日：2012-07-23
申请人： Richard P. Volant , Mukta G. Farooq , Kevin S. Petrarca
发明人： Richard P. Volant , Mukta G. Farooq , Kevin S. Petrarca
IPC分类号： H01L21/768
CPC分类号： H01L21/76879 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L24/16 , H01L24/29 , H01L24/82 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/29 , H01L2224/29298 , H01L2224/9202 , H01L2224/92144 , H01L2225/06541 , H01L2225/06575 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/05552 , H01L2924/00
摘要： A microelectronic assembly and related method of forming a through hole extending through a first chip and a second chip are provided. The first and second chip have confronting faces, metallic features join the first and second chips leaving a gap chips . A first etch creates a hole through the first chip. The hole has a first wall extending in a vertical direction, and a second wall sloping inwardly from the first wall to an inner opening to expose the gap. Material of the first or second chips exposed within the hole is sputtered to form a wall in the gap. A second etch extends the hole into the second chip. An electrically conductive through silicon via can then be formed extending through the first chip, the wall between the chips and into the second chip.
摘要翻译：提供了形成贯穿第一芯片和第二芯片的通孔的微电子组件和相关方法。第一和第二芯片具有面对面，金属特征连接第一和第二芯片留下间隙芯片。第一蚀刻通过第一芯片产生孔。孔具有沿垂直方向延伸的第一壁和从第一壁向内倾斜到内部开口的第二壁，以露出间隙。暴露在孔内的第一或第二芯片的材料被溅射以在间隙中形成壁。第二蚀刻将孔延伸到第二芯片中。然后可以形成延伸穿过第一芯片，芯片之间的壁并进入第二芯片的导电硅通孔。

97. 发明申请

US20130026606A1 TSV PILLAR AS AN INTERCONNECTING STRUCTURE 有权
标题翻译： TSV柱作为互连结构
公开(公告)号：US20130026606A1
公开(公告)日：2013-01-31
申请号：US13194214
申请日：2011-07-29
申请人： Mukta G. Farooq , Troy L. Graves-Abe , William F. Landers , Kevin S. Petrarca , Richard P. Volant
发明人： Mukta G. Farooq , Troy L. Graves-Abe , William F. Landers , Kevin S. Petrarca , Richard P. Volant
IPC分类号： H01L23/522 , H01L21/98 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/10126 , H01L2224/11009 , H01L2224/1145 , H01L2224/11452 , H01L2224/11602 , H01L2224/11612 , H01L2224/11614 , H01L2224/11616 , H01L2224/13009 , H01L2224/13017 , H01L2224/13022 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13147 , H01L2224/13565 , H01L2224/13583 , H01L2224/13584 , H01L2224/13647 , H01L2224/13655 , H01L2224/13679 , H01L2224/1368 , H01L2224/13681 , H01L2224/13683 , H01L2224/13684 , H01L2224/13687 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/32225 , H01L2224/73203 , H01L2224/81191 , H01L2224/81801 , H01L2224/8385 , H01L2224/9202 , H01L2224/92143 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/351 , H01L2924/3512 , H01L2924/00014 , H01L2924/04953 , H01L2924/0496 , H01L2924/01074 , H01L2924/04941 , H01L2924/053 , H01L2924/014 , H01L2924/00012 , H01L2224/11 , H01L2924/00
摘要： The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.
摘要翻译：本发明包括用于构建具有可用作互连结构的TSV柱的芯片的处理方法和结果的结构的实施例。该过程包括在TSV和衬底之间沉积TSV和衬底之间的双重扩散阻挡层。 TSV然后从衬底的背面露出，使得TSV的至少一部分从衬底突出，并且可以用作用于将芯片连接到另一表面的接触件。所产生的TSV是刚性的，高导电性的，可以放置在紧密连接的接触网格中，并减少CTE失配的影响。

98. 发明申请

US20120326309A1 OPTIMIZED ANNULAR COPPER TSV 有权
标题翻译：优化的环形铜片TSV
公开(公告)号：US20120326309A1
公开(公告)日：2012-12-27
申请号：US13167107
申请日：2011-06-23
申请人： PAUL S ANDRY , Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Emily R. Kinser , Cornelia K. Tsang , Richard P. Volant
发明人： PAUL S ANDRY , Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Emily R. Kinser , Cornelia K. Tsang , Richard P. Volant
IPC分类号： H01L23/48 , H01L21/283
CPC分类号： H01L21/76846 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.
摘要翻译：本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。衬底限定沟槽的内侧壁和外侧壁，该侧壁分隔5至10微米的距离。包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。基板厚度可以为60微米或更小。具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。

99. 发明申请

US20120304138A1 CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY 有权
标题翻译：电路设计检查三维芯片技术
公开(公告)号：US20120304138A1
公开(公告)日：2012-11-29
申请号：US13113421
申请日：2011-05-23
申请人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
发明人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.
摘要翻译：一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。转换电路设计可以通过标准验证检查进行处理。该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。如果相应的设计单元对应于镜像侧，则设计单元被镜像。然后所有镜像单元格以正确的顺序与未设计的设计单元合并。合并设计通过标准验证检查进行处理。该工具还可以为两个相邻的芯片创建终端金属摘要。其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

100. 发明申请

US20120280395A1 3-D Integration using Multi Stage Vias 有权
标题翻译：使用多级通道的3-D集成
公开(公告)号：US20120280395A1
公开(公告)日：2012-11-08
申请号：US13101268
申请日：2011-05-05
申请人： Mukta G. Farooq , Troy L. Graves-Abe
发明人： Mukta G. Farooq , Troy L. Graves-Abe
IPC分类号： H01L23/48 , H01L21/3205
CPC分类号： H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV is can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias.
摘要翻译：可以形成TSV，其具有通过顶部衬底表面形成的顶部截面，以及通过底部衬底表面形成的底部截面。顶部截面可以具有对应于设计规则的最小横截面，并且顶部截面深度可对应于可工作的纵横比。顶部通孔可以被填充或插入，以便可以继续顶部处理。底部通孔可以具有更大的横截面，以便于形成穿过其中的导电路径。底部部分通孔从顶部部分通孔的背面延伸到底部，并且在基板变薄之后形成。可以通过在从接合的顶部和底部部分通孔去除牺牲填充材料之后形成导电路径来完成TSV。

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