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91. 发明授权

US07323418B1 Etch-back process for capping a polymer memory device 有权
标题翻译：用于封盖聚合物存储器件的蚀刻工艺
公开(公告)号：US07323418B1
公开(公告)日：2008-01-29
申请号：US11102004
申请日：2005-04-08
申请人： Minh Van Ngo , Angela T. Hui , Sergey D. Lopatin
发明人： Minh Van Ngo , Angela T. Hui , Sergey D. Lopatin
IPC分类号： H01L21/302
CPC分类号： G11C13/0016 , G11C13/0014 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/1608 , H01L45/1683 , H01L51/0591
摘要： The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides tiny electrical contacts necessary for the proper functioning of polymer memory devices that utilize the vias. In one instance of the present invention, one or more via openings are formed in a dielectric layer to expose an underlying layer. A polymer layer is then formed within the via on the underlying layer with a top electrode material layer deposited over the polymer layer, filling the remaining portion of the via. Excess portions of the top electrode material are then removed by an etching process to form an electrode cap that provides an electrical contact point for the polymer memory element.
摘要翻译：本发明利用回蚀工艺来提供用于聚合物存储元件的电极帽。这允许聚合物存储元件形成在嵌入在衬底上形成的层中的通孔内。通过利用回蚀工艺，本发明提供了利用通孔的聚合物存储器件的适当功能所需的微小电触点。在本发明的一个实例中，在电介质层中形成一个或多个通孔以露出下层。然后在下层上的通孔内形成聚合物层，其中沉积在聚合物层上的顶部电极材料层填充通孔的剩余部分。然后通过蚀刻工艺去除顶部电极材料的多余部分以形成提供聚合物存储元件的电接触点的电极帽。

92. 发明授权

US07091088B1 UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing 有权
标题翻译：用于减少BEOL处理中的存储器件中的电荷存储层的UV诱导的充电的UV阻挡蚀刻停止层
公开(公告)号：US07091088B1
公开(公告)日：2006-08-15
申请号：US10861437
申请日：2004-06-03
申请人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
发明人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
IPC分类号： H01L21/336
CPC分类号： H01L23/53295 , H01L21/76829 , H01L27/115 , H01L27/11568 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing over the charge trapping dielectric flash memory cell at least one UV-protective layer; forming at least one layer over the at least one UV-protective layer; and etching the at least one layer to form an opening therein with an etchant species selective to stop on a layer below the at least one UV-protective layer, wherein the UV-protective layer comprises a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷捕获电介质闪存单元上沉积至少一个UV保护层; 在所述至少一个UV保护层上形成至少一层; 以及蚀刻所述至少一个层以在其中形成具有选择性地停留在所述至少一个UV保护层下方的层上的蚀刻剂物质的开口，其中所述UV保护层包括基本上不透紫外线的材料。

93. 发明授权

US07038320B1 Single damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的单镶嵌一体化方案
公开(公告)号：US07038320B1
公开(公告)日：2006-05-02
申请号：US09785445
申请日：2001-02-20
申请人： Lu You , Fei Wang , Minh Van Ngo
发明人： Lu You , Fei Wang , Minh Van Ngo
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76804 , H01L21/76814 , H01L21/76834
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A second etch stop layer can also be disposed between the first diffusion barrier layer and the first etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上并与第一扩散阻挡层隔开，并且介电层设置在第一蚀刻停止层上。通孔也可以有圆角。第二蚀刻停止层也可以设置在第一扩散阻挡层和第一蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

94. 发明授权

US06989563B1 Flash memory cell with UV protective layer 有权
标题翻译：具有UV保护层的闪存单元
公开(公告)号：US06989563B1
公开(公告)日：2006-01-24
申请号：US10770260
申请日：2004-02-02
申请人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
发明人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , H01L23/53295 , H01L23/552 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric flash memory cell and depositing over the planarized interlevel dielectric layer at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷俘获电介质闪存单元上沉积和平坦化层间电介质层，并在平坦化的层间电介质层上沉积至少一个UV保护层，UV保护层包括基本上不透紫外线的材料。

95. 发明授权

US06787458B1 Polymer memory device formed in via opening 失效
标题翻译：聚合物存储器件形成在通孔中
公开(公告)号：US06787458B1
公开(公告)日：2004-09-07
申请号：US10614397
申请日：2003-07-07
申请人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
发明人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
IPC分类号： H01L2144
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译：本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

96. 发明授权

US06730587B1 Titanium barrier for nickel silicidation of a gate electrode 有权
标题翻译：用于栅电极的硅化硅的钛屏障
公开(公告)号：US06730587B1
公开(公告)日：2004-05-04
申请号：US09731006
申请日：2000-12-07
申请人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George Kluth
发明人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George Kluth
IPC分类号： H01L213205
CPC分类号： H01L29/4941 , H01L21/28052 , H01L29/665
摘要： Nickel silicidation of a gate electrode is controlled using a titanium barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of titanium thereon and an upper polycrystalline silicon layer on the titanium layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and a titanium silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.
摘要翻译：使用钛阻挡层来控制栅电极的镍硅化。实施例包括在钛层上形成包括下多晶硅层，钛层和上多晶硅层的栅极电极结构，沉积镍层和硅化物，由此将上多晶硅层转变为硅化镍，形成防止镍与下部多晶硅层反应的硅化钛阻挡层。

97. 发明授权

US06713874B1 Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics 有权
标题翻译：在有机掺杂的石英玻璃层间电介质上具有双重自然封盖/电弧层的半导体器件
公开(公告)号：US06713874B1
公开(公告)日：2004-03-30
申请号：US09817050
申请日：2001-03-27
申请人： Dawn M. Hopper , Lu You , Minh Van Ngo
发明人： Dawn M. Hopper , Lu You , Minh Van Ngo
IPC分类号： H01L2348
CPC分类号： H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L23/3171 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Degradation of organic-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on the organic-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.
摘要翻译：通过在层间电介质膜上形成双重性质覆盖/ ARC层，在制造期间降低有机掺杂石英玻璃低k层间电介质的降解显着降低，并提高亚微米特征的分辨率。在有机掺杂的石英玻璃层间电介质上原位形成封盖/ ARC层。封盖/ ARC层的原位形成提供了强烈粘附的封盖/ ARC层，其形成与传统封盖和ARC层相比较少的处理步骤。

98. 发明授权

US06706576B1 Laser thermal annealing of silicon nitride for increased density and etch selectivity 有权
标题翻译：氮化硅的激光热退火以提高密度和蚀刻选择性
公开(公告)号：US06706576B1
公开(公告)日：2004-03-16
申请号：US10096741
申请日：2002-03-14
申请人： Minh Van Ngo , Angela Hui
发明人： Minh Van Ngo , Angela Hui
IPC分类号： H01L2100
CPC分类号： H01L27/11521 , H01L21/3185 , H01L21/76802 , H01L21/76825 , H01L21/76828 , H01L21/76829 , H01L27/115
摘要： The density of a deposited silicon nitride layer is increased by laser thermal annealing in N2, thereby increasing etch selectivity with respect to an overlying oxide and, hence, avoiding damage to underlying silicide layers and gates. Embodiments include laser thermal annealing a silicon nitride layer deposited as an etch stop layer, e.g., in fabricating EEPROMs, to increase its density by up to about 8%, thereby increasing its etch selectivity with respect to an overlying BPSG layer to about {fraction (1/12)} to about {fraction (1/14)}.
摘要翻译：沉积的氮化硅层的密度通过在N 2中的激光热退火而增加，从而相对于上覆氧化物增加了蚀刻选择性，因此避免了对下面的硅化物层和栅极的损害。实施例包括激光热退火沉积为蚀刻停止层的氮化硅层，例如在制造EEPROM中，将其密度增加高达约8％，从而将其相对于上覆的BPSG层的蚀刻选择性增加到约{部分（ 1/12至约{部分（1/14。

99. 发明授权

US06638861B1 Method of eliminating voids in W plugs 失效
标题翻译：消除W插头空隙的方法
公开(公告)号：US06638861B1
公开(公告)日：2003-10-28
申请号：US09986263
申请日：2001-11-08
申请人： Minh Van Ngo , Eric Paton
发明人： Minh Van Ngo , Eric Paton
IPC分类号： H01L2144
CPC分类号： C25D5/50 , H01L21/76882
摘要： Reliable contacts/vias are formed by filling an opening in a dielectric layer with W and laser thermal annealing to eliminate or significantly reduce voids. Embodiments include depositing W to fill a contact/via opening in an interlayer dielectric, laser thermal annealing in N2 to elevate the temperature of the W filling the contact/via opening and reflow the W thereby eliminating voids. Embodiments include conducting CMP either before or subsequent to laser thermal annealing.
摘要翻译：通过用W和激光热退火填充介电层中的开口来形成可靠的触点/通孔，以消除或显着减少空隙。实施例包括沉积W以填充层间电介质中的接触/通孔开口，在N2中进行激光热退火以升高填充接触/通孔开口的W的温度并回流W，从而消除空隙。实施例包括在激光热退火之前或之后进行CMP。

100. 发明授权

US06599827B1 Methods of forming capped copper interconnects with improved electromigration resistance 有权
标题翻译：形成具有改善的电迁移阻力的封盖铜互连的方法
公开(公告)号：US06599827B1
公开(公告)日：2003-07-29
申请号：US09846273
申请日：2001-05-02
申请人： Minh Van Ngo , Steven C. Avanzino , Amit P. Marathe , Hartmut Ruelke
发明人： Minh Van Ngo , Steven C. Avanzino , Amit P. Marathe , Hartmut Ruelke
IPC分类号： H01L214763
CPC分类号： H01L21/76834 , H01L21/76883
摘要： The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by pumping out the deposition chamber after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma, introducing NH3 and N2 into the deposition chamber, and then ramping up the introduction of SiH4 prior to initiating deposition of a silicon nitride capping layer. Embodiments include ramping up the introduction of SiH4 in two stages prior to initiating plasma enhanced chemical vapor deposition of the silicon nitride capping layer.
摘要翻译：通过在用含氨的等离子体处理暴露的Cu或Cu合金的平坦化表面之后，通过泵出沉积室来显着改善封盖的Cu或Cu合金互连的电迁移电阻，将NH 3和N 2引入沉积室，然后斜坡在开始沉积氮化硅覆盖层之前引入SiH4。实施例包括在引发氮化硅覆盖层的等离子体增强化学气相沉积之前分两阶段引入SiH4。

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