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91. 发明授权

US06396108B1 Self-aligned double gate silicon-on-insulator (SOI) device 有权
标题翻译：自对准双栅极绝缘体上硅（SOI）器件
公开(公告)号：US06396108B1
公开(公告)日：2002-05-28
申请号：US09711328
申请日：2000-11-13
申请人： Zoran Krivokapic , Matthew Buynoski
发明人： Zoran Krivokapic , Matthew Buynoski
IPC分类号： H01L21336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A self-aligned double gate transistor, comprising: a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region, and having a first side and a second side, the first side and the second side having a first gate oxide and a second gate oxide, respectively, formed thereon; a first silicon gate abutting said first side of said channel region on said insulator; and a second silicon gate abutting said second side of said channel on said insulator. A method for manufacturing a double gate transistor device, comprising: providing a substrate having a buried oxide region; depositing a first nitride mask layer having a pattern overlying a silicon region; forming a trench in said substrate with a depth to said buried oxide; forming a gate oxide in said trench; depositing polysilicon in said trench; depositing a second nitride mask layer having a pattern formed perpendicular to said first nitride mask; etching the portion of said polysilicon not underlying said first or second nitride layers; removing said second nitride layer; and implanting an impurity into exposed portions of polysilicon in said trench and of said silicon-on-insulator substrate underlying said second nitride layer.
摘要翻译：一种自对准双栅极晶体管，包括：隔离层上的第一硅部分，所述硅部分中形成有源极区和由沟道区分离的漏极区，并且具有第一侧和第二侧，并且第二侧分别具有形成在其上的第一栅极氧化物和第二栅极氧化物; 邻接所述绝缘体上的所述沟道区域的第一侧的第一硅栅极; 以及与所述绝缘体上的所述沟道的所述第二侧邻接的第二硅栅极。1.一种制造双栅极晶体管器件的方法，包括：提供具有掩埋氧化物区域的衬底; 沉积具有覆盖硅区域的图案的第一氮化物掩模层; 在所述衬底中形成具有所述掩埋氧化物的深度的沟槽; 在所述沟槽中形成栅极氧化物; 在所述沟槽中沉积多晶硅; 沉积具有垂直于所述第一氮化物掩模形成的图案的第二氮化物掩模层; 蚀刻所述多晶硅的不在所述第一或第二氮化物层下面的部分; 去除所述第二氮化物层; 以及将杂质注入所述沟槽中的多晶硅的暴露部分和所述第二氮化物层下面的所述绝缘体上硅衬底。

92. 发明授权

US06380589B1 Semiconductor-on-insulator (SOI) tunneling junction transistor SRAM cell 有权
标题翻译：绝缘体上半导体（SOI）隧道结晶体管SRAM单元
公开(公告)号：US06380589B1
公开(公告)日：2002-04-30
申请号：US09774138
申请日：2001-01-30
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： H01L2701
CPC分类号： H01L27/11
摘要： A tunneling junction transistor (TJT) SRAM cell device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The SOI TJT SRAM cell device includes a first gate and a second gate stacked over one of the active regions. The first gate defines a channel interposed between a source and a drain formed within one of the active regions. The second gate includes a plurality of thin nitride layer interposed between an undoped region and the first gate electrode, a side gate electrode, and a polysilicon layer. The plurality of thin nitride layers form tunneling junctions between the electrodes. The SOI TJT SRAM cell device is electrically coupled respectively to a first and a second node; and a contact plug adjacent and in electrical contact with at least one of the source and the drain.
摘要翻译：在绝缘体上半导体（SOI）衬底上形成有埋置氧化物（BOX）层的隧道结结晶体管（TJT）SRAM单元器件，以及设置在BOX层上的有源层，该有源层具有由隔离沟槽限定的有源区。 SOI TJT SRAM单元器件包括堆叠在一个有源区上的第一栅极和第二栅极。第一栅极限定介于源极和漏极之间的通道，其形成在一个有源区域内。第二栅极包括介于未掺杂区域和第一栅极电极，侧栅极电极和多晶硅层之间的多个薄氮化物层。多个薄氮化物层在电极之间形成隧道结。 SOI TJT SRAM单元器件分别电耦合到第一和第二节点; 以及与源极和漏极中的至少一个相邻并与其接触的接触塞。

93. 发明授权

US06372563B1 Self-aligned SOI device with body contact and NiSi2 gate 有权
标题翻译：具有体接触和NiSi2栅极的自对准SOI器件
公开(公告)号：US06372563B1
公开(公告)日：2002-04-16
申请号：US09614894
申请日：2000-07-12
申请人： Zoran Krivokapic , Shekhar Pramanick
发明人： Zoran Krivokapic , Shekhar Pramanick
IPC分类号： H01L2100
CPC分类号： H01L21/28052 , H01L21/2022 , H01L21/28097 , H01L21/28123 , H01L29/0653 , H01L29/4238 , H01L29/4975 , H01L29/66651
摘要： A self-aligned SOI device with body contact and silicide gate. The SOI device is formed using an ordinary substrate such as silicon. A silicide gate is self-aligned and formed from re-crystallization of nickel and amorphous silicon. The self-aligned silicide gate includes gate contact areas, and is self-aligned with respect to the gate opening, the source and drain regions and a nitride isolation layer. Nickel spacers deposited adjacent the isolation layer, and amorphous silicon deposited between the nickel spacers, form the self-aligned silicide gate through a silicidation process.
摘要翻译：具有体接触和硅化物栅的自对准SOI器件。 SOI器件使用诸如硅的普通衬底形成。硅化物栅极是自对准的，并由镍和非晶硅的再结晶形成。自对准硅化物栅极包括栅极接触区域，并且相对于栅极开口，源极和漏极区域以及氮化物隔离层自对准。沉积在隔离层附近的镍间隔物和沉积在镍间隔物之间的非晶硅通过硅化工艺形成自对准的硅化物栅极。

94. 发明授权

US06304836B1 Worst case design parameter extraction for logic technologies 失效
标题翻译：最恶劣案例设计参数提取逻辑技术
公开(公告)号：US06304836B1
公开(公告)日：2001-10-16
申请号：US09112606
申请日：1998-07-09
申请人： Zoran Krivokapic , William D. Heavlin
发明人： Zoran Krivokapic , William D. Heavlin
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： The present invention provides for more realistic worst case extreme determinations for an integrated circuit as compared to conventional techniques. In particular, the present invention provides a framework which affords for improved linkage between semiconductor manufacturing process parameters and an integrated circuit designed based on the electrical properties of cells making up the integrated circuit. The present invention divides an integrated circuit into simple standard cells and more complex cells. For simple standard cells (e.g., XOR, NAND, NOR, inverter), a pre-modeling step is performed to model the simple standard cell as a circuit in order to obtain gate delay and power consumption distributions related thereto. Such pre-modeling affords for more accurate semiconductor physical parameters to be employed to generate the normalized distribution of the integrated circuit which in turn provides for better worst case extremes. More complex cells are modeled with I/V curves distributions for understanding the effects of semiconductor device attribute choices, such as channel length, effects of “guard band” or manufacturability of such devices. As a result of the present invention, IC circuits may be manufactured with more realistic or practical worst case extreme parameters and thus, more densely designed and manufactured without substantially sacrificing operability.
摘要翻译：与常规技术相比，本发明提供了对于集成电路的更实际的最坏情况极限确定。特别地，本发明提供了一种框架，其提供了半导体制造工艺参数之间的改进的连接以及基于构成集成电路的电池的电特性而设计的集成电路。本发明将集成电路分为简单的标准单元和更复杂的单元。对于简单的标准单元（例如，XOR，NAND，NOR，逆变器），执行预建模步骤以将简单标准单元建模为电路，以便获得与其相关的门延迟和功耗分布。这种预建模提供了用于产生集成电路的归一化分布的更准确的半导体物理参数，其进而提供了更好的最坏情况极限。通过I / V曲线分布对更复杂的单元进行建模，以了解半导体器件属性选择的影响，例如通道长度，“保护带”的影响或这些器件的可制造性。作为本发明的结果，IC电路可以制造成具有更现实或实际的最坏情况的极限参数，并且因此更加密集地设计和制造而基本上不牺牲可操作性。

95. 发明授权

US06296709B1 Temperature ramp for vertical diffusion furnace 有权
标题翻译：垂直扩散炉的温度斜坡
公开(公告)号：US06296709B1
公开(公告)日：2001-10-02
申请号：US09511796
申请日：2000-02-23
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： C23C1600
CPC分类号： H01L21/67109 , Y10S438/935
摘要： An improved vertical diffusion furnace for semiconductor manufacturing processes is provided. Temperature and flow rate management enables more uniform temperature distribution across the wafer during ramp up and ramp down, thereby preventing wafer warp.
摘要翻译：提供了一种用于半导体制造工艺的改进的垂直扩散炉。温度和流量管理使得在斜坡上升和下降期间在晶片上更均匀的温度分布，从而防止晶片翘曲。

96. 发明授权

US06291832B1 Resonant tunneling diode latch 有权
标题翻译：谐振隧道二极管锁存器
公开(公告)号：US06291832B1
公开(公告)日：2001-09-18
申请号：US09557679
申请日：2000-04-25
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： H01L2106
CPC分类号： B82Y10/00 , H01L29/66151 , H01L29/882
摘要： A method/system for forming a resonant tunneling diode latch is disclosed. The method/system comprises the steps of forming a gate on a silicon substrate, the silicon substrate having at least one SOI layer disposed therein, providing an oxide spacer over the gate, providing a first ion implant in a first region of the silicon substrate, and then providing an oxide layer. The method further comprises polishing the oxide back to the gate, removing the gate, providing a second ion implant in a second region of the silicon substrate wherein the first and second regions have an undoped portion of silicon there between. According to the present invention, the method/system for forming a resonant tunneling diode latch in an SOI substrate that is easily implemented and results in an increased throughput of resonant tunneling diode devices.
摘要翻译：公开了一种用于形成谐振隧穿二极管锁存器的方法/系统。所述方法/系统包括以下步骤：在硅衬底上形成栅极，所述硅衬底具有设置在其中的至少一个SOI层，在所述栅极上提供氧化物间隔物，在所述硅衬底的第一区域中提供第一离子注入，然后提供氧化物层。该方法还包括将氧化物抛光回到栅极，去除栅极，在硅衬底的第二区域中提供第二离子注入，其中第一和第二区域之间具有未掺杂的硅部分。根据本发明，在SOI衬底中形成谐振隧穿二极管锁存器的方法/系统容易实现，并且导致谐振隧道二极管器件的吞吐量增加。

97. 发明授权

US06255711B1 Encroachless LOCOS isolation 失效
标题翻译：无门LOCOS隔离
公开(公告)号：US06255711B1
公开(公告)日：2001-07-03
申请号：US09398916
申请日：1999-09-16
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： H01L2900
CPC分类号： H01L21/76202
摘要： The present invention provides a fabrication process for fabricating an integrated circuit substrate structure having LOCOS isolation areas formed such that oxidation encroachment at an active surface region patterned on the substrate is less than 0.1 &mgr;m. The fabrication process includes various process steps for forming a 0.75 &mgr;m. to 1.0 &mgr;m layer of silicon dioxide (SiO2) over thin layers of silicon dioxide (0.01 &mgr;m. to 0.05 &mgr;m) and silicon nitride (0.05 &mgr;m. to 0.10 &mgr;m) over a surface region of the substrate to form a protective stack/passivation layers over a surface region of the silicon substrate. The protected substrate surface region is useable for fabricating a microelectronic circuit device, such as a MOS transistor, or a flash memory device. Adjacent the protective stack, a silicon nitride spacer region is formed to effectively widen the protected substrate surface region. The silicon nitride spacer region limits the encroachment of oxide, commonly called bird's beak growth of oxide, into the active surface region beneath the spacer and protective stack. The resulting structure, after removal of the silicon nitride and other passivation layers, is one having an oxide encroachment region that is less than 0.1 &mgr;m.
摘要翻译：本发明提供一种用于制造集成电路衬底结构的制造方法，其具有形成为使得在衬底上图案化的有源表面区域上的氧化侵入小于0.1μm的LOCOS隔离区域。制造工艺包括用于形成0.75毫米的各种工艺步骤。在二氧化硅（0.01mum至0.05mum）的薄层上的2.0μm二氧化硅层（SiO 2）和氮化硅（0.05μm至0.10μm），以形成保护层/钝化层在硅衬底的表面区域上。受保护的衬底表面区域可用于制造诸如MOS晶体管或闪存器件的微电子电路器件。邻近保护层，形成氮化硅间隔区以有效地加宽受保护的衬底表面区域。氮化硅间隔区将氧化物的侵蚀（通常称为鸟类的氧化物生长）限制在间隔物和保护层下面的有源表面区域中。在除去氮化硅和其它钝化层之后，所得到的结构是具有小于0.1μm的氧化物侵入区域的结构。

98. 发明授权

US06194293B1 Channel formation after source and drain regions are formed 有权
标题翻译：形成源极和漏极区之后的沟道形成
公开(公告)号：US06194293B1
公开(公告)日：2001-02-27
申请号：US09318519
申请日：1999-05-25
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： H01L21425
CPC分类号： H01L29/66537 , H01L21/26586 , H01L21/823807 , H01L29/105
摘要： A channel region is formed in a device after the source and drain regions are formed by implanting ions into the channel region with a tilt angle using multiple rotations. A rapid thermal annealing step is performed to activate the channel dopant. Because the source and drain regions are already formed, a relatively low temperature, e.g., 990 to 1010 degrees Celsius, and short, e.g., 1 to 5 seconds, rapid thermal annealing step may be performed to activate the channel region. Thus, the dopant concentration in the channel region may be well localized and accurately controlled.
摘要翻译：在通过使用多次旋转以倾斜角将离子注入沟道区域形成源极和漏极区域之后，在器件中形成沟道区域。执行快速热退火步骤以激活沟道掺杂剂。因为源极和漏极区域已经形成，所以可以执行比较低的温度，例如990至1010摄氏度，以及短的，例如1至5秒的快速热退火步骤以激活沟道区域。因此，通道区域中的掺杂剂浓度可以很好地定位并且被精确地控制。

99. 发明授权

US6091123A Self-aligned SOI device with body contact and NiSi.sub.2 gate 失效
公开(公告)号：US6091123A
公开(公告)日：2000-07-18
申请号：US93580
申请日：1998-06-08
申请人： Zoran Krivokapic , Shekhar Pramanick
发明人： Zoran Krivokapic , Shekhar Pramanick
IPC分类号： H01L21/20 , H01L21/28 , H01L21/336 , H01L29/06 , H01L29/423 , H01L29/49
CPC分类号： H01L29/66651 , H01L21/2022 , H01L21/28097 , H01L21/28123 , H01L29/0653 , H01L29/4238 , H01L29/4975
摘要： A self-aligned SOI device with body contact and silicide gate. The SOI device is formed using an ordinary substrate such as silicon. A silicide gate is self-aligned and formed from re-crystallization of nickel and amorphous silicon. The self-aligned silicide gate includes gate contact areas, and is self-aligned with respect to the gate opening, the source and drain regions and a nitride isolation layer. Nickel spacers deposited adjacent the isolation layer, and amorphous silicon deposited between the nickel spacers, form the self-aligned silicide gate through a silicidation process.

100. 发明授权

US6080630A Method for forming a MOS device with self-compensating V.sub.T -implants 有权
标题翻译：用于形成具有自补偿VT植入物的MOS器件的方法
公开(公告)号：US6080630A
公开(公告)日：2000-06-27
申请号：US243014
申请日：1999-02-03
申请人： Ognjen Milic-Strkalj , Richard Rouse , Zoran Krivokapic
发明人： Ognjen Milic-Strkalj , Richard Rouse , Zoran Krivokapic
IPC分类号： H01L21/225 , H01L21/336 , H01L29/10
CPC分类号： H01L29/6659 , H01L21/2253 , H01L29/1045
摘要： The present invention provides a method for forming a MOS device having self-compensating threshold adjust implants and reduced junction capacitance. A semiconductor substrate of a first conductivity type is provided. A gate oxide is formed on the surface of the semiconductor substrate, and a polysilicon gate is formed on the surface of the gate oxide. A first implant of a dopant of the first conductivity type is performed so as to form self-compensating implant regions in the semiconductor substrate on opposite sides of the gate. Disposable sidewall spacers are then formed around the polysilicon gate. A second implant of a dopant of a second conductivity type is performed so as to create highly-doped source/drain regions which are self-aligned to the sidewall spacers. The substrate with self-compensating implant regions and the highly-doped source/drain regions is then subject to a rapid thermal anneal (RTA) process so as to activate the dopant in the self-compensating implant regions and the highly-doped source/drain regions. The dopant within the self-compensating regions diffuses laterally under the polysilicon gate to define pockets. Thereafter, the disposable sidewall spacers are removed. Finally, a third implant of a dopant of the second conductivity type is performed so as to create lightly-doped source/drain regions in the self-compensating implant regions on opposite sides of the gate.
摘要翻译：本发明提供一种用于形成具有自补偿阈值调整植入物和降低结电容的MOS器件的方法。提供第一导电类型的半导体衬底。在半导体衬底的表面上形成栅极氧化物，并且在栅极氧化物的表面上形成多晶硅栅极。执行第一导电类型的掺杂剂的第一注入，以在栅极的相对侧上的半导体衬底中形成自补偿注入区域。然后在多晶硅栅极周围形成一次性侧壁间隔物。执行第二导电类型的掺杂剂的第二注入，以便产生与侧壁间隔物自对准的高掺杂源/漏区。然后，具有自补偿注入区域和高掺杂源极/漏极区域的衬底经受快速热退火（RTA）工艺，以激活自补偿注入区域中的掺杂剂和高掺杂源极/漏极地区。自补偿区域内的掺杂剂在多晶硅栅极下方横向扩散以形成凹穴。此后，去除一次性侧壁间隔物。最后，执行第二导电类型的掺杂剂的第三注入，以在栅极的相对侧上的自补偿注入区域中产生轻掺杂的源极/漏极区域。

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