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    • 91. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US08350326B2
    • 2013-01-08
    • US12839895
    • 2010-07-20
    • Yoshiaki FukuzumiRyota KatsumataMasaru KitoMasaru KidohHiroyasu TanakaHideaki Aochi
    • Yoshiaki FukuzumiRyota KatsumataMasaru KitoMasaru KidohHiroyasu TanakaHideaki Aochi
    • H01L29/792
    • H01L29/7926H01L21/28282H01L27/11578H01L27/11582H01L29/42344H01L29/66833
    • According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structural bodies, first and second semiconductor pillars, a memory unit connection portion, a selection unit stacked structural body, first and second selection unit semiconductor pillars, a selection unit connection portion, and first to fifth interconnections. The semiconductor pillars pierce the stacked structural bodies. The first and second interconnections are connected to the first and second semiconductor pillars, respectively. The memory unit connection portion connects the first and second semiconductor pillars. The selection unit semiconductor pillars pierce the selection unit stacked structural body. The third and fourth interconnections are connected to the first and second selection unit semiconductor pillars, respectively. The selection unit connection portion connects the first and second selection unit semiconductor pillars. The fifth interconnection is connected to the third interconnection on a side opposite to the selection unit stacked structural body.
    • 根据一个实施例,非易失性半导体存储器件包括第一和第二堆叠结构体,第一和第二半导体柱,存储单元连接部分,选择单元堆叠结构体,第一和第二选择单元半导体柱,选择单元连接部分 ,以及第一至第五互连。 半导体支柱刺穿堆叠的结构体。 第一和第二互连分别连接到第一和第二半导体柱。 存储单元连接部连接第一和第二半导体柱。 选择单元半导体柱刺穿选择单元堆叠结构体。 第三和第四互连分别连接到第一和第二选择单元半导体柱。 选择单元连接部分连接第一和第二选择单元半导体柱。 第五互连在与选择单元堆叠结构体相反的一侧连接到第三互连。
    • 99. 发明授权
    • Non-volatile semiconductor storage device and method of manufacturing the same
    • 非易失性半导体存储装置及其制造方法
    • US07910432B2
    • 2011-03-22
    • US12393509
    • 2009-02-26
    • Hiroyasu TanakaMasaru KidohRyota KatsumataMasaru KitoYoshiaki FukuzumiHideaki AochiYasuyuki Matsuoka
    • Hiroyasu TanakaMasaru KidohRyota KatsumataMasaru KitoYoshiaki FukuzumiHideaki AochiYasuyuki Matsuoka
    • H01L21/336
    • H01L27/11578H01L27/11582
    • Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction. Respective ends of the plurality of first conductive layers in the first direction are formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers are formed in an area immediately above the top layer of the first conductive layers, and the plurality of first conductive layers and the plurality of second conductive layers are covered with a protection insulation layer that is formed continuously with the plurality of first conductive layers and the second conductive layers.
    • 每个存储器串包括:在垂直方向上延伸到衬底的第一柱状半导体层; 多个第一导电层,其形成为夹着具有电荷陷阱层的绝缘层并以二维方式扩展; 第二柱状半导体层,其与所述第一柱状半导体层的顶表面接触并且在垂直方向上延伸到所述衬底; 以及多个第二导电层,其形成为与第二柱状半导体层夹着绝缘层,并且形成为沿与垂直方向正交的第一方向延伸的条纹图案。 多个第一导电层的第一方向的端部相对于彼此分步地形成,多个第二导电层的整体形成在第一导电层的顶层的正上方的区域中, 并且多个第一导电层和多个第二导电层被与多个第一导电层和第二导电层连续形成的保护绝缘层覆盖。