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91. 发明授权

US06625660B1 Multiprocessor speculation mechanism for efficiently managing multiple barrier operations 有权
标题翻译：用于有效管理多个屏障操作的多处理器推测机制
公开(公告)号：US06625660B1
公开(公告)日：2003-09-23
申请号：US09588605
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F1516
CPC分类号： G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3867
摘要： Disclosed is a method of operation within a processor that permits load instructions to be issued speculatively. An instruction sequence is received that includes multiple barrier instructions and a load instruction that follows the barrier instructions in the instruction sequence. In response to the multiple barrier instructions, barrier operations are issued on an interconnect coupled to the processor. Also, while the barrier operations are pending, a load request associated with the load instruction is speculatively issued. When the load request is issued, a flag is set to indicate that it was speculatively issued. The flag is reset when acknowledgments of all the barrier operations are received. Data that is returned before the acknowledgments are received is temporarily held and forwarded to the register and/or execution unit of the processor only after the acknowledgments are received. If a snoop invalidate is detected for the speculatively issued load request before completion of the barrier operations, the data is discarded and the load request is re-issued.
摘要翻译：公开了一种在处理器内操作的方法，其允许以推测方式发布加载指令。接收包括多个屏障指令和跟随指令序列中的屏障指令的加载指令的指令序列。响应于多个屏障指令，在耦合到处理器的互连上发出屏障操作。此外，当屏障操作正在等待时，推测性地发出与加载指令相关联的加载请求。当发出加载请求时，会设置一个标志来指示它被推测发出。当接收到所有屏障操作的确认时，该标志被复位。在接收到确认之前返回的数据被暂时保存，并且在接收到确认之后被转发到处理器的寄存器和/或执行单元。如果在完成屏障操作之前，对于推测发出的加载请求检测到窥探无效，则丢弃数据并重新发出加载请求。

92. 发明授权

US08195880B2 Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow 有权
标题翻译：信息处理系统，具有双重缓存中的负载操作的即时调度，具有双重调度到写入/读取数据流
公开(公告)号：US08195880B2
公开(公告)日：2012-06-05
申请号：US12424255
申请日：2009-04-15
申请人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F12/0811
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供双调度点到二级高速缓冲存储器的双缓存组。

93. 发明授权

US08015358B2 System bus structure for large L2 cache array topology with different latency domains 失效
标题翻译：具有不同延迟域的大二级缓存阵列拓扑的系统总线结构
公开(公告)号：US08015358B2
公开(公告)日：2011-09-06
申请号：US12207393
申请日：2008-09-09
申请人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.
摘要翻译：一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。

94. 发明授权

US07987320B2 Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation 有权
标题翻译：缓存机制和方法，用于避免对不良受害者选择和回收受害者选择操作
公开(公告)号：US07987320B2
公开(公告)日：2011-07-26
申请号：US11951783
申请日：2007-12-06
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/125 , G06F2212/1032
摘要： A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the bad victim selection addressed are recovery from selection of a deleted member and recovery from use of LRU state bits that do not map to a member within the congruence class. When LRU victim selection logic generates an output vector identifying a victim, the output vector is checked to ensure that it is a valid vector (non-null) and that it is not pointing to a deleted member. When the output vector is not valid or points to a deleted member, the LRU victim selection logic is triggered to re-start the victim selection process.
摘要翻译：一种方法，装置和计算机，用于在高速缓存的受害者选择期间识别对不良受害者的选择，并从这种不良受害者选择中恢复，而不会导致系统崩溃或中止向前进行受害者选择过程。所解决的不良受害者选择之一是从选择已删除成员的恢复以及使用不映射到同余类中的成员的LRU状态位进行恢复。当LRU受害者选择逻辑生成识别受害者的输出向量时，检查输出向量以确保它是有效向量（非空值），并且不指向已删除的成员。当输出向量无效或指向被删除成员时，LRU受害者选择逻辑被触发以重新启动受害者选择过程。

95. 发明申请

US20090006759A1 SYSTEM BUS STRUCTURE FOR LARGE L2 CACHE ARRAY TOPOLOGY WITH DIFFERENT LATENCY DOMAINS 失效
标题翻译：具有不同LATENCY域的大型L2高速缓存阵列的系统总线结构
公开(公告)号：US20090006759A1
公开(公告)日：2009-01-01
申请号：US12207445
申请日：2008-09-09
申请人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.
摘要翻译：一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。

96. 发明授权

US07343455B2 Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation 有权
标题翻译：缓存机制和方法，用于避免对不良受害者选择和回收受害者选择操作
公开(公告)号：US07343455B2
公开(公告)日：2008-03-11
申请号：US11054394
申请日：2005-02-09
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/123 , G06F2212/1032
摘要： A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the bad victim selection addressed are recovery from selection of a deleted member and recovery from use of LRU state bits that do not map to a member within the congruence class. When LRU victim selection logic generates an output vector identifying a victim, the output vector is checked to ensure that it is a valid vector (non-null) and that it is not pointing to a deleted member. When the output vector is not valid or points to a deleted member, the LRU victim selection logic is triggered to re-start the victim selection process.
摘要翻译：一种方法，装置和计算机，用于在高速缓存的受害者选择期间识别对不良受害者的选择，并从这种不良受害者选择中恢复，而不会导致系统崩溃或中止向前进行受害者选择过程。所解决的不良受害者选择之一是从选择已删除成员的恢复以及使用不映射到同余类中的成员的LRU状态位进行恢复。当LRU受害者选择逻辑生成识别受害者的输出向量时，检查输出向量以确保它是有效向量（非空值），并且不指向已删除的成员。当输出向量无效或指向被删除成员时，LRU受害者选择逻辑被触发以重新启动受害者选择过程。

97. 发明授权

US07069494B2 Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism 有权
标题翻译：在ECC保护机制中应用特殊ECC矩阵解决卡位故障
公开(公告)号：US07069494B2
公开(公告)日：2006-06-27
申请号：US10418549
申请日：2003-04-17
申请人： Robert Alan Cargnoni , Guy Lynn Guthrie , Kirk Samuel Livingston , William John Starke
发明人： Robert Alan Cargnoni , Guy Lynn Guthrie , Kirk Samuel Livingston , William John Starke
IPC分类号： H03M13/11
CPC分类号： G06F11/1064 , H03M13/13
摘要： A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N−1)-bit error detection. In the illustrative embodiment, the ECC matrix has an odd number of bits set in each row thereof. In the case of an ECC protected mechanism such as a memory device, these properties facilitate the use of an inversion bit for correcting hard faults in the stored data. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array. The corresponding inversion bit for this entry is accordingly set to indicate that the data as currently stored is inverted. Thereafter, the data is re-read from the array, and if the error was due to a hard fault (stuck bit), it will appear correct (after applying the polarity indicated by the inversion bit), since the inversion will have changed the value of the defective bit to the stuck value. The inversion bit may be part of the data itself. In this case, one of the columns in the ECC matrix corresponds to the inversion bit, and each bit in that column of the matrix is set. In the case of an ECC protected mechanism such as a system bus, once a stuck bit condition is detected, the sending device can elect to send data such that the polarity of the data for that bit is always flipped to match the logic level of the stuck value on the wire. This approach allows for full single-bit correct, double-bit detect even in the presence of a stuck bit.
摘要翻译：一种通过将具有多个位N的数据应用于纠错码（ECC）矩阵来校正诸如高速缓存或系统总线的计算机系统的ECC保护机制中的错误的方法，以产生错误检测综合征，其中 ECC矩阵具有多个行和列，给定列对应于相应的一个数据位，并且所选择的位在每个列和每行的ECC矩阵中被设置，使得对于ECC矩阵的编码允许N位纠错和（N-1）位错误检测。在说明性实施例中，ECC矩阵在其每行中设置奇数位。在诸如存储器件的ECC保护机制的情况下，这些属性有利于使用反转位来校正所存储的数据中的硬故障。当检测到错误并且在其被校正之后，校正的数据被反转，然后被重写到高速缓存阵列。因此，该条目的相应的反转位被设置为指示当前存储的数据被反转。此后，数据从阵列重新读取，如果错误是由于硬故障（卡位）引起的，则会显示正确的（应用反转位指示的极性后），因为反转将会改变有缺陷位的值到卡住值。反转位可能是数据本身的一部分。在这种情况下，ECC矩阵中的列之一对应于反转比特，矩阵的该列中的每个比特被设置。在诸如系统总线的ECC保护机制的情况下，一旦检测到卡位状态，发送设备就可以选择发送数据，使得该位的数据的极性总是被翻转以匹配在线上卡住了值。这种方法允许完全单位正确，双位检测，即使存在卡位。

98. 发明授权

US07039832B2 Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems 失效
标题翻译：稳定的系统可靠性通过收缩制造级芯片测试在微处理器/系统上的实时操作
公开(公告)号：US07039832B2
公开(公告)日：2006-05-02
申请号：US10313329
申请日：2002-12-05
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A method and system are disclosed for running a manufacturing-level test program on an installed processor by interrupting processor execution of a non-test process. Periodic execution of the manufacturing-level test program allows the processor to continually self-test during normal function operation, in order to facilitate proper maintenance and function of the processor and a data processing system of which the processor is a part.
摘要翻译：公开了一种方法和系统，用于通过中断非测试过程的处理器执行来在安装的处理器上运行制造级测试程序。制造级测试程序的定期执行允许处理器在正常功能操作期间不间断地进行自检，以便促进处理器和处理器作为其一部分的数据处理系统的适当维护和功能。

99. 发明授权

US06629209B1 Cache coherency protocol permitting sharing of a locked data granule 失效
标题翻译：缓存一致性协议允许共享锁定的数据粒子
公开(公告)号：US06629209B1
公开(公告)日：2003-09-30
申请号：US09437185
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized by replacing frequently-occurring and inefficient MESI code sequences with improved sequences using modified cache states.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。额外的高速缓存状态允许通过使用修改的高速缓存状态替换具有改进的序列的频繁出现的和低效的MESI码序列来优化高速缓存状态转换序列。

100. 发明授权

US06625701B1 Extended cache coherency protocol with a modified store instruction lock release indicator 失效
标题翻译：扩展缓存一致性协议，具有修改后的存储指令锁定释放指示器
公开(公告)号：US06625701B1
公开(公告)日：2003-09-23
申请号：US09437183
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1214
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an indicator bit with the cache store command which specifically indicates whether the store also acts as a lock-release.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。特别地，由于多个处理器竞争相同的高速缓存行，所以丢失了大量的处理器时间，这确定了另一个处理器的高速缓存行锁定是否已被释放，并尝试在该另一个处理器仍然拥有的情况下保留该高速缓存行。优选实施例提供具有高速缓存存储命令的指示符位，其特别地指示存储还是否用作锁定释放。

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