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91. 发明授权

US07166896B2 Cross diffusion barrier layer in polysilicon 有权
标题翻译：多晶硅中的交叉扩散阻挡层
公开(公告)号：US07166896B2
公开(公告)日：2007-01-23
申请号：US10228839
申请日：2002-08-26
申请人： Sanh D. Tang , Chih-Chen Cho , Robert Burke , Anuradha Iyengar , Eugene R. Gifford
发明人： Sanh D. Tang , Chih-Chen Cho , Robert Burke , Anuradha Iyengar , Eugene R. Gifford
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L21/823842 , H01L21/823871 , H01L27/1104 , H01L29/4941 , Y10S257/903 , Y10S438/927
摘要： A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of second conductivity type. The cross diffusion barrier layer includes a combination of silicon and nitrogen. The cross diffusion barrier layer adequately prevents cross diffusion between the first and second gate portions while causing no substantial increase in the resistance of the gate layer.
摘要翻译：半导体器件包括夹在栅极层和电极层之间的交叉扩散阻挡层。栅极层具有与第二导电类型的掺杂多晶硅的第二栅极部分相邻的第一导电类型的掺杂多晶硅的第一栅极部分。交叉扩散阻挡层包括硅和氮的组合。交叉扩散阻挡层充分地防止了第一和第二栅极部分之间的交叉扩散，同时不会显着增加栅极层的电阻。

92. 发明授权

US07153731B2 Method of forming a field effect transistor with halo implant regions 有权
标题翻译：用卤素注入区域形成场效应晶体管的方法
公开(公告)号：US07153731B2
公开(公告)日：2006-12-26
申请号：US10236662
申请日：2002-09-05
申请人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
发明人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
IPC分类号： H01L21/336 , H01L21/331 , H01L21/76 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/66651 , H01L21/26533 , H01L29/0653 , H01L29/41766 , H01L29/66636
摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。源极/漏极区域形成在沟道区域的相对侧上。绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。形成场效应晶体管的方法包括提供绝缘体上半导体衬底，所述衬底包括在绝缘材料层上形成的半导体材料层。半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去，从而在半导体材料层和绝缘材料层中产生空隙。半导体通道材料形成在空隙内。相邻的源极/漏极区域横向靠近通道材料提供。在通道材料上形成一个栅极。集成电路包括体半导体衬底。其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。考虑其他方面。

93. 发明授权

US07112482B2 Method of forming a field effect transistor 有权
公开(公告)号：US07112482B2
公开(公告)日：2006-09-26
申请号：US10901538
申请日：2004-07-28
申请人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
发明人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
IPC分类号： H01L21/8238
CPC分类号： H01L29/66651 , H01L21/26533 , H01L29/0653 , H01L29/41766 , H01L29/66636
摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

94. 发明申请

US20060198199A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法及其工作方法
公开(公告)号：US20060198199A1
公开(公告)日：2006-09-07
申请号：US11162330
申请日：2005-09-07
申请人： Saysamone Pittikoun , Houng-Chi Wei , Chih-Chen Cho
发明人： Saysamone Pittikoun , Houng-Chi Wei , Chih-Chen Cho
IPC分类号： G11C16/04
CPC分类号： H01L29/42324 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L29/40114
摘要： A non-volatile memory having a plurality of memory units each including a select unit and a memory unit is provided. The select unit is disposed on the substrate. The memory cell is disposed on one sidewall of the select unit and the substrate. The select unit includes a gate disposed on the substrate and a first gate dielectric layer disposed between the gate and the substrate. The memory cell includes a pair of floating gate disposed on the substrate, a control gate disposed on the upper surface of the floating gates, an inter-gate dielectric layer disposed between the floating gate and the control gate, a tunneling dielectric layer disposed between the floating gate and the substrate and a second gate dielectric layer disposed between the bottom of the control gate and the substrate.
摘要翻译：提供具有多个存储单元的非易失性存储器，每个存储器单元包括选择单元和存储器单元。选择单元设置在基板上。存储单元设置在选择单元和基板的一个侧壁上。选择单元包括设置在基板上的栅极和设置在栅极和基板之间的第一栅极电介质层。所述存储单元包括设置在所述衬底上的一对浮置栅极，设置在所述浮置栅极的上表面上的控制栅极，设置在所述浮置栅极和所述控制栅极之间的栅极间电介质层，浮置栅极和衬底以及设置在控制栅极的底部和衬底之间的第二栅极电介质层。

95. 发明申请

US20060197231A1 Backend metallization method and device obtained therefrom 审中-公开
公开(公告)号：US20060197231A1
公开(公告)日：2006-09-07
申请号：US11403923
申请日：2006-04-14
申请人： Chih-Chen Cho
发明人： Chih-Chen Cho
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76816 , H01L21/76829 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from etching an area within a dielectric material near a conductive plug. The mask may be formed of a nitride. Conductive material is then deposited withinan etched via and is contacted with the conductive plug.

96. 发明申请

US20060186481A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法及其工作方法
公开(公告)号：US20060186481A1
公开(公告)日：2006-08-24
申请号：US11161312
申请日：2005-07-29
申请人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
发明人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
IPC分类号： H01L29/76
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A non-volatile memory having many memory cell columns is provided. Each memory cell column includes a plurality of memory cells formed on a substrate. A deep p-type well is disposed in the substrate and an n-type well is disposed on the deep p-type well. A shallow p-type well isolated by device isolation structures is disposed on the n-type well. A select unit is disposed on one side of each memory cell column. An n-type source region is disposed in the substrate adjacent to the select unit. An n-type drain region is disposed in the substrate on the other side of the memory cell column. A bit line is disposed on the substrate. The bit line connects with the n-type drain region through a conductive plug. The conductive plug penetrates the junction between the n-type drain region and the shallow p-type well and forms a short between them.
摘要翻译：提供了具有许多存储单元列的非易失性存储器。每个存储单元列包括形成在基板上的多个存储单元。在衬底中设置深p型阱，在深p型阱上设置n型阱。通过器件隔离结构隔离的浅P型阱设置在n型阱上。选择单元设置在每个存储单元列的一侧。 n型源极区域设置在与选择单元相邻的衬底中。在存储单元列的另一侧的衬底中设置n型漏极区。位线设置在基板上。位线通过导电插头与n型漏极区域连接。导电插塞穿透n型漏极区和浅P型阱之间的结，并在它们之间形成短路。

97. 发明授权

US07095083B2 Methods for making semiconductor structures having high-speed areas and high-density areas 有权
公开(公告)号：US07095083B2
公开(公告)日：2006-08-22
申请号：US11105775
申请日：2005-04-13
申请人： Chih-Chen Cho , Zhongze Wang
发明人： Chih-Chen Cho , Zhongze Wang
IPC分类号： H01L29/76
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/105 , H01L27/1052 , H01L27/11
摘要： Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a metallization layer simultaneously into the high-density area and the high-speed area. The metallization layer includes a combination of substances and compounds that reduce vertical resistance, reduce horizontal resistance, and inhibit cross-diffusion.

98. 发明申请

US20060170026A1 NON-VOLATILE MEMORY AND FABRICATING METHOD AND OPERATING METHOD THEREOF 有权
标题翻译：非挥发性记忆及其制作方法及其操作方法
公开(公告)号：US20060170026A1
公开(公告)日：2006-08-03
申请号：US11162116
申请日：2005-08-29
申请人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
发明人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.
摘要翻译：提供非易失性存储器。衬底在其中具有至少两个隔离结构以限定有效区域。一个井位于基板中。浅掺杂区域位于井中。至少两个堆叠的栅极结构位于衬底上。袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。辅助栅极层位于堆叠栅极结构之间的衬底上。栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。

99. 发明申请

US20060097325A1 One-time programmable read only memory and operating method thereof 有权
标题翻译：一次性可编程只读存储器及其操作方法
公开(公告)号：US20060097325A1
公开(公告)日：2006-05-11
申请号：US11144471
申请日：2005-06-02
申请人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
发明人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
IPC分类号： H01L29/94
CPC分类号： H01L27/112 , H01L27/11206
摘要： A one-time programmable read only memory is provided. The memory includes a substrate, a select transistor, an electrode and a dielectric layer. The select transistor is formed on the substrate. The electrode is formed over the source region of the select transistor. The dielectric layer is formed between the electrode and the source region of the select transistor. Digital data is stored in the memory through the breakdown or not of the dielectric layer.
摘要翻译：提供一次性可编程只读存储器。存储器包括衬底，选择晶体管，电极和电介质层。选择晶体管形成在基板上。电极形成在选择晶体管的源极区域上。介电层形成在选择晶体管的电极和源极区之间。数字数据通过绝缘层的击穿而不是存储在存储器中。

100. 发明授权

US07037775B2 Applying epitaxial silicon in disposable spacer flow 失效
公开(公告)号：US07037775B2
公开(公告)日：2006-05-02
申请号：US10861438
申请日：2004-06-03
申请人： Chih-Chen Cho , Er-Xuan Ping
发明人： Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L27/10894 , H01L21/28525 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L27/105 , H01L27/10873 , H01L27/11526 , H01L27/11546 , H01L29/66636
摘要： A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

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