专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US5184208A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5184208A
公开(公告)日：1993-02-02
申请号：US640584
申请日：1991-01-14
申请人： Toshiyuki Sakuta , Kazuyuki Miyazawa , Satoshi Oguchi , Aizo Kaneda , Masao Mitani , Shozo Nakamura , Kunihiko Nishi , Gen Murakami
发明人： Toshiyuki Sakuta , Kazuyuki Miyazawa , Satoshi Oguchi , Aizo Kaneda , Masao Mitani , Shozo Nakamura , Kunihiko Nishi , Gen Murakami
IPC分类号： H01L23/29 , H01L23/495
CPC分类号： H01L23/293 , H01L23/4951 , H01L2224/05554 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48599 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/181
摘要： A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.
摘要翻译：半导体器件与半导体芯片相连，该半导体芯片在与其前表面或第一主表面的中心位置相对应的部分处具有多个接合焊盘;半导体芯片，覆盖在半导体芯片上并具有开口与接合焊盘相对应，多个有机绝缘膜上的引线，以及密封或封装这些成分的成型树脂。

92. 发明授权

US5047983A Semiconductor storage device with redundancy arrangement 失效
标题翻译：具有冗余布置的半导体存储设备
公开(公告)号：US5047983A
公开(公告)日：1991-09-10
申请号：US586399
申请日：1990-09-20
申请人： Hidetoshi Iwai , Kazuyuki Miyazawa
发明人： Hidetoshi Iwai , Kazuyuki Miyazawa
IPC分类号： G06F11/16 , G11C11/401 , G11C29/00 , G11C29/04
CPC分类号： G11C29/842
摘要： In a semiconductor storage device having a spare memory, an input address signal is checked by an address comparator circuit. When the input address signal indicates an address which is to be relieved, the spare memory is selected instead of a memory array on the basis of the output of the address comparator circuit at that time. In conventional system, the access time of the semiconductor memory is restricted substantially by the operating time of the address comparator circuit during this operation. Accordingly, for enabling a quick access of the semiconductor memory, an address signal to be supplied to the address comparator circuit is output from a proceeding stage circuit of a plurality of amplification stages which form an address buffer circuit.
摘要翻译：在具有备用存储器的半导体存储装置中，由地址比较器电路检查输入地址信号。当输入地址信号指示要被释放的地址时，基于当时的地址比较器电路的输出，选择备用存储器而不是存储器阵列。在常规系统中，半导体存储器的访问时间基本上受到地址比较器电路在此操作期间的操作时间的限制。因此，为了能够快速访问半导体存储器，从地址比较器电路提供的地址信号从形成地址缓冲电路的多个放大级的前级电路输出。

93. 发明授权

US4992985A Method for selectively initiating/terminating a test mode in an address multiplexed DRAM and address multiplexed DRAM having such a capability 失效
标题翻译：用于在地址多路复用DRAM中选择性地启动/终止测试模式的方法，以及具有这种能力的地址多路复用DRAM
公开(公告)号：US4992985A
公开(公告)日：1991-02-12
申请号：US319693
申请日：1989-03-07
申请人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
发明人： Kazuyuki Miyazawa , Katsuhiro Shimohigashi , Jun Etoh , Katsutaka Kimura
IPC分类号： G11C11/401 , G01R31/317 , G11C29/00 , G11C29/14 , G11C29/46
CPC分类号： G11C29/46 , G01R31/31701
摘要： An address multiplexed dynamic RAM device is provided which is capable of initiating (setting) and terminating (resetting) the test mode in response to the signal level combinations of the row address and column address strobe signals with the write enable signal, which signal level combinations correspond to those which are otherwise left unused in the normal operating mode thereby obviating the requirement of an additional external control signal terminal. Such initiating of the test mode can be effected by setting the RAS signal of the DRAM at a logic "low" level when the CAS signal and the WE signal are at a logic "low" level. Clearing or resetting thereof is effected by the same combination sequence, except that the WE signal is at a logic "high" level. The setting or initiating of a test mode is also implemented by the additional combination of one of the row address signal bits, e.g. the most significant bit.

94. 发明授权

US4943949A Semiconductor memory including means for noise suppression 失效
标题翻译：半导体存储器包括用于噪声抑制的装置
公开(公告)号：US4943949A
公开(公告)日：1990-07-24
申请号：US802197
申请日：1985-11-25
申请人： Yasunori Yamaguchi , Kanji Oishi , Kazuyuki Miyazawa
发明人： Yasunori Yamaguchi , Kanji Oishi , Kazuyuki Miyazawa
IPC分类号： G11C11/401 , G11C11/4096
CPC分类号： G11C11/4096
摘要： A half precharge type dynamic RAM has a pair of data lines to which a plurality of dynamic memory cells are coupled. The paired data lines are set in advance before a read operation at a reference potential which is equal to one half of the supply voltage. One of the paired data lines is switched to have a higher or lower level than the reference potential by the memory cell selected. The potential difference applied between the paired data lines is amplified by the operation of a sense amplifier. Here, an address selecting MOSFET in the memory cell has a gate capacitance which will undesirably couple a word line and the data lines. As a result, one of the data lines has its level changed in an undesired manner. The noise inparted between the paired data lines by such coupling noise components can be substantially neglected by adopting a dummy MOSFET which operates to impart coupling noise components corresponding to the noise components caused by the address selecting MOSFET gate capacitance.
摘要翻译：半预充电型动态RAM具有耦合多个动态存储单元的一对数据线。在等于电源电压的一半的参考电位的读取操作之前，预先设置成对的数据线。成对数据线中的一个被选择的存储器单元切换到比参考电位更高或更低的电平。通过读出放大器的操作来放大配对数据线之间的电位差。这里，存储单元中的地址选择MOSFET具有将不期望地耦合字线和数据线的栅极电容。结果，其中一条数据线的水平以不期望的方式改变。通过这样的耦合噪声分量在成对数据线之间插入的噪声可以通过采用虚拟MOSFET来实质上被忽略，该虚拟MOSFET用于赋予与由地址选择MOSFET栅极电容引起的噪声分量相对应的耦合噪声分量。

95. 发明授权

US07906670B2 Phosphorylcholine group containing compound and surface modifying agent composed of such compound 有权
标题翻译：含有磷酰胆碱的化合物和由这种化合物组成的表面改性剂
公开(公告)号：US07906670B2
公开(公告)日：2011-03-15
申请号：US10580874
申请日：2004-12-01
申请人： Yousuke Toujo , Kazuyuki Miyazawa , Taketoshi Kanda , Hiroshi Kutsuna , Kenichi Sakuma , Masayoshi Wada , Yukimitsu Suda
发明人： Yousuke Toujo , Kazuyuki Miyazawa , Taketoshi Kanda , Hiroshi Kutsuna , Kenichi Sakuma , Masayoshi Wada , Yukimitsu Suda
IPC分类号： C07F9/02
CPC分类号： B01J20/286 , B01J20/28004 , B01J20/28019 , B01J20/28057 , B01J20/28078 , B01J20/289 , B01J20/3092 , B01J20/3204 , B01J20/3246 , B01J20/3257 , B01J20/3259 , B01J2220/54 , B01J2220/58 , B01L3/569 , B01L2300/163 , C07F9/091
摘要： A phosphorylcholine group-containing chemical compound represented by the following formula (1). In this formula, m denotes 2-6 and n denotes 1-4.X1, X2, and X3, independent of each other, denote a methoxy group, ethoxy group, or halogen. Up to two of X1, X2, and X3 can be any of the following groups: a methyl group, ethyl group, propyl group, isopropyl group, butyl group, or isobutyl group.R is one of the structures in the following formulas (2)-(4) (the chemical compound of formula (1) in the structures of the following formulas (2)-(4) is expressed as A-R—B). In formulas (2)-(4), L is 1-6, P is 1-3.Also a surface modifier consisting of the aforementioned phosphorylcholine group-containing chemical compound, modified powder treated with said surface modifier, a chromatography packing consisting of a modified carrier treated with said surface modifier, a filter treated with said surface modifier, and a glass device treated with said surface modifier.
摘要翻译：由下式（1）表示的含磷酰胆碱基的化合物。在该式中，m表示2-6，n表示1-4。 X1，X2和X3彼此独立地表示甲氧基，乙氧基或卤素。 X1，X2，X3中的2个以上可以是甲基，乙基，丙基，异丙基，丁基或异丁基中的任一种。 R是下式（2） - （4）中的结构之一（下式（2） - （4）的结构中的式（1）的化合物表示为A-R-B）。在式（2） - （4）中，L为1-6，P为1-3。还有一种由上述含磷酰胆碱基团的化合物组成的表面改性剂，用所述表面改性剂处理的改性粉末，由用所述表面改性剂处理的改性载体组成的色谱填料，用所述表面改性剂处理的过滤器和处理过的玻璃装置与所述表面改性剂。

96. 发明授权

US07821285B2 Liquid crystal display apparatus and testing method for liquid crystal display apparatus 有权
标题翻译：液晶显示装置及液晶显示装置的试验方法
公开(公告)号：US07821285B2
公开(公告)日：2010-10-26
申请号：US11811774
申请日：2007-06-12
申请人： Hideaki Kawaura , Kazutoshi Shimizume , Naoki Ando , Kazuyuki Miyazawa , Katsuhisa Hirano , Noriaki Horiguchi , Osamu Akimoto
发明人： Hideaki Kawaura , Kazutoshi Shimizume , Naoki Ando , Kazuyuki Miyazawa , Katsuhisa Hirano , Noriaki Horiguchi , Osamu Akimoto
IPC分类号： G01R31/00
CPC分类号： G09G3/006 , G09G3/3611 , G09G2320/0295
摘要： Disclosed herein is a liquid crystal display apparatus, including, a pixel array section, a first data line, a second data line, a writing unit, a voltage supply control unit, a data line short-circuiting unit, a reading out unit, and a testing unit.
摘要翻译：本发明公开了一种液晶显示装置，包括：像素阵列部，第一数据线，第二数据线，写单元，电压供给控制部，数据线短路部，读出部，一个测试单元。

97. 发明授权

US07674782B2 Phosphorylcholine group-containing compound and method for producing same 有权
标题翻译：含有磷酰胆碱的化合物及其制备方法
公开(公告)号：US07674782B2
公开(公告)日：2010-03-09
申请号：US11664670
申请日：2005-11-28
申请人： Yukimitsu Suda , Kazuyuki Miyazawa
发明人： Yukimitsu Suda , Kazuyuki Miyazawa
IPC分类号： A61K31/685 , C07F9/02 , C08F30/02
CPC分类号： C07F9/091
摘要： The present invention is a phosphorylcholine-containing chemical compound represented by the following formula (1) or (2). (CH3)3N+CH2CH2PO4−CH2COOH (1) (CH3)3N+CH2CH2PO4−CH2COONa (2) The object of the present invention is to provide a new phosphorylcholine-containing compound that is useful as a surface treatment agent or a source material of a surface treatment agent. Another object is to provide a manufacturing method that has a high industrial utility value.
摘要翻译：本发明是由下式（1）或（2）表示的含磷酰胆碱的化合物。（CH3）3N + CH2CH2PO4-CH2COOH（1）（CH3）3N + CH2CH2PO4-CH2COONa（2）本发明的目的是提供一种新的含磷酰胆碱的化合物，其可用作表面处理剂或源材料表面处理剂。另一个目的是提供具有很高工业实用价值的制造方法。

98. 发明申请

US20080300369A1 Eye Lens Material and Method of Manufacturing Thereof 失效
标题翻译：眼镜材料及其制造方法
公开(公告)号：US20080300369A1
公开(公告)日：2008-12-04
申请号：US10593682
申请日：2005-05-18
申请人： Yukimitsu Suda , Kazuyuki Miyazawa , Kazuhiko Ishihara
发明人： Yukimitsu Suda , Kazuyuki Miyazawa , Kazuhiko Ishihara
IPC分类号： C08L67/00
CPC分类号： C08J7/12 , A61F2/16 , A61F2002/1699 , A61L27/28 , G02B1/043
摘要： The present invention is a method of manufacturing an eye lens material having a process in which a phosphorylcholine group-containing chemical compound represented by the following formula (1) is reacted and covalently bonded to the surface of an eye lens material having hydroxyl groups wherein the chemical compound represented by the following formula (2) is reacted and covalently bonded through ester-bonding to the eye lens material in an organic solvent.The object of the present invention is to provide an eye lens material that prevents protein adsorption and a method of manufacturing thereof.
摘要翻译：本发明是一种眼镜透镜材料的制造方法，其具有下述通式（1）所示的含磷酰胆碱基的化合物与具有羟基的眼晶状体材料的表面反应并共价键合的方法，其中，由下式（2）表示的化合物通过酯键在有机溶剂中与眼晶体材料反应并共价键合。本发明的目的是提供一种防止蛋白质吸附的眼用透镜材料及其制造方法。

99. 发明申请

US20080038221A1 Method For Producing Protein Adsorption-Preventing Ocular Lens Material 失效
标题翻译：生产蛋白质吸附防止眼部镜片材料的方法
公开(公告)号：US20080038221A1
公开(公告)日：2008-02-14
申请号：US10592772
申请日：2005-05-18
申请人： Yukimitsu Suda , Kazuyuki Miyazawa , Kazuhiko Ishihara
发明人： Yukimitsu Suda , Kazuyuki Miyazawa , Kazuhiko Ishihara
IPC分类号： A61K31/80
CPC分类号： C08J7/12 , A61F2/16 , G02B1/043
摘要： The present invention is a method of manufacturing an eye lens material having a process in which a phosphorylcholine group-containing chemical compound represented by the following formula (1) is reacted and covalently bonded onto the surface of an eye lens material wherein a chemical compound having an end amino group is introduced to said eye lens material and then the chemical compound represented by the following formula (2) or (3) is introduced through said chemical compound having an end amino group. The object of the present invention is to provide a method of manufacturing a contact lens that prevents protein adsorption. n denotes a natural number 1-18.
摘要翻译：本发明是一种眼透镜材料的制造方法，其具有以下处理：将由下式（1）表示的含磷酰胆碱基的化合物反应并共价键合到眼晶状体材料的表面上，其中具有将末端氨基引入所述眼晶状体材料中，然后通过具有末端氨基的化合物引入由下式（2）或（3）表示的化合物。本发明的目的是提供一种制造防止蛋白质吸附的隐形眼镜的方法。 n表示自然数1-18。

100. 发明授权

US07257026B2 Non-volatile multi-level semiconductor flash memory device and method of driving same 有权
标题翻译：非易失性多级半导体闪存器件及其驱动方法
公开(公告)号：US07257026B2
公开(公告)日：2007-08-14
申请号：US11418017
申请日：2006-05-05
申请人： Naoki Yamada , Hiroshi Sato , Tetsuya Tsujikawa , Kazuyuki Miyazawa
发明人： Naoki Yamada , Hiroshi Sato , Tetsuya Tsujikawa , Kazuyuki Miyazawa
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C7/1006 , G11C8/00 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2211/5621
摘要： In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.
摘要翻译：在其中设置多个阈值以将多电平数据存储在存储单元中的非易失性半导体存储器件中，根据地址信号或控制信号将多位数据的位分别写入存储器单元阅读和删除。具体地说，存储器阵列被构造成可以通过X，Y和Z的三维地址来访问，存储器单元中的多位数据由Z地址区分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式