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91. 发明授权

US06614119B1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06614119B1
公开(公告)日：2003-09-02
申请号：US09521771
申请日：2000-03-09
申请人： Michio Asahina , Junichi Takeuchi , Naohiro Moriya , Kazuki Matsumoto
发明人： Michio Asahina , Junichi Takeuchi , Naohiro Moriya , Kazuki Matsumoto
IPC分类号： H01L2940
CPC分类号： H01L21/76814 , H01L21/28518 , H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/76837 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877
摘要： A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300° C. to 550° C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.; (e) a step of forming a first aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the wetting layer at a temperature of no more than 200° C.; and (f) a step of forming a second aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the first aluminum layer at a temperature of at least 300° C.
摘要翻译：一种具有接触结构的半导体器件，其可以显示出最高级的覆盖范围，而不引起空隙或接线不连续性，使用铝或铝合金作为通孔的导电物质。制造半导体器件的方法包括：对于在半导体衬底上的第一布线区域上方的布线区域中的至少一层的以下步骤（a）至（f）：（a）形成通孔的步骤形成在半导体衬底上的第一布线区域上方的第二层间电介质; （b）通过减压热处理和基板温度在300℃至550℃下除去层间电介质中包含的气体组分的脱气步骤; （c）在层间电介质和通孔的表面上形成润湿层的步骤; （d）将基板冷却至不超过100℃的温度; （e）在不超过200℃的温度下形成包含铝和合金中的铝的第一铝层的步骤，其中铝是润湿层上的主要成分; 以及（f）在至少300℃的温度下形成第一铝层的步骤，所述第二铝层包括铝和合金之一，其中铝是第一铝层上的主要成分。

92. 发明授权

US6144097A Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US6144097A
公开(公告)日：2000-11-07
申请号：US220590
申请日：1998-12-28
申请人： Michio Asahina , Junichi Takeuchi , Naohiro Moriya , Kazuki Matsumoto
发明人： Michio Asahina , Junichi Takeuchi , Naohiro Moriya , Kazuki Matsumoto
IPC分类号： H01L21/28 , H01L21/316 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76846 , H01L21/76843 , H01L23/485 , H01L23/53223 , H01L2924/0002 , Y10S438/927
摘要： A semiconductor device comprising a semiconductor substrate including an electronic element, interlayer dielectric (silicon oxide layer and BPSG layer) formed on the semiconductor substrate, a contact hole formed in the interlayer dielectric, a barrier layer formed on the interlayer dielectric and contact hole, and a wiring layer formed on the barrier layer. In the barrier layer, metal oxide (titanium oxide) are scattered in an island-like configuration. The barrier layer is formed by depositing a layer that is used to form the barrier layer and then introducing oxygen into the layer. The step is achieved by depositing a layer for the barrier layer, exposing the layer in oxygen plasma under reduced pressure, and subjecting the layer to the thermal processing, or, alternatively by depositing a layer for the barrier layer and subjecting the layer to thermal processing in an atmosphere of oxygen. The semiconductor device of the present invention has a barrier layer with excellent barrier properties.
摘要翻译：一种半导体器件，包括形成在半导体衬底上的电子元件，层间电介质（氧化硅层和BPSG层）的半导体衬底，形成在层间电介质中的接触孔，形成在层间电介质和接触孔上的阻挡层，以及形成在阻挡层上的布线层。在阻挡层中，金属氧化物（氧化钛）以岛状构造分散。阻挡层通过沉积用于形成阻挡层然后将氧引入层中的层而形成。该步骤通过沉积阻挡层的层，在减压下在氧等离子体中暴露层，并对该层进行热处理，或者通过沉积用于阻挡层的层并使该层进行热处理来实现在氧气氛中。本发明的半导体装置具有阻隔性优异的阻挡层。

93. 发明授权

US6137176A Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6137176A
公开(公告)日：2000-10-24
申请号：US104403
申请日：1998-06-25
申请人： Yukio Morozumi , Michio Asahina , Naohiro Moriya , Kazuki Matsumoto , Eiji Suzuki
发明人： Yukio Morozumi , Michio Asahina , Naohiro Moriya , Kazuki Matsumoto , Eiji Suzuki
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/532 , H01L29/78 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76828 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02271 , H01L21/02274 , H01L21/31051 , H01L21/31625 , H01L21/76801 , H01L21/76804 , H01L21/76814 , H01L21/76819 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76843 , H01L21/76856 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L23/5329 , H01L2924/0002
摘要： A process of forming an interlayer dielectric on a semiconductor substrate including an electronic element includes:forming first silicon oxide layer by reacting a silicon compound including hydrogen with hydrogen peroxide using a chemical vapor deposition method;forming a porous second silicon oxide layer by reacting between a compound including an impurity, silicon compounds, and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method; andannealing at a temperature of 300.degree. C. to 850.degree. C. to make the first and second silicon oxide layers more fine-grained. The first silicon oxide layer is formed at a temperature that is lower than that required of a BPSG film, and it has superior self-flattening characteristics in itself.
摘要翻译：在包括电子元件的半导体衬底上形成层间电介质的工艺包括：通过化学气相沉积法使包括氢的硅化合物与过氧化氢反应形成第一氧化硅层; 通过使用化学气相沉积法在包括杂质，硅化合物和至少一种选自氧的化合物和包括氧的化合物中的化合物之间反应形成多孔的第二氧化硅层; 并在300℃至850℃的温度下进行退火，以使第一和第二氧化硅层更细粒度。第一氧化硅层形成在低于BPSG膜所要求的温度下，其本身具有优异的自扁平化特性。

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