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91. 发明授权

US06219295B1 Semiconductor memory with transfer buffer structure 有权
标题翻译：半导体存储器与传输缓冲结构
公开(公告)号：US06219295B1
公开(公告)日：2001-04-17
申请号：US09526349
申请日：2000-03-16
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C5/025 , G11C7/10
摘要： A plurality of sense amplifiers are provided between a plurality of memory cell arrays having a plurality of memory cells. These sense amplifiers are connected to bit lines of the respective memory cell arrays by array selection switches. Each of the sense amplifiers is connected to data lines by column switches. An array control portion is provided at each of the memory cell arrays. This array control portion selectively controls the array selection switches and column switches to transmit the data in an arbitrary memory cell in a memory cell array to the data lines through the sense amplifier.
摘要翻译：在具有多个存储单元的多个存储单元阵列之间提供多个读出放大器。这些读出放大器通过阵列选择开关连接到各个存储单元阵列的位线。每个读出放大器通过列开关连接到数据线。在每个存储单元阵列中设置阵列控制部分。该阵列控制部分选择性地控制阵列选择开关和列开关，以通过读出放大器将存储单元阵列中的任意存储单元中的数据传输到数据线。

92. 发明授权

US6144615A Synchronous dynamic random access memory 有权
公开(公告)号：US6144615A
公开(公告)日：2000-11-07
申请号：US418958
申请日：1999-10-14
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4096 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C7/10 , G11C11/4096 , G11C7/103 , G11C7/1072
摘要： A synchronous DRAM has cell arrays arranged in matrix, divided into banks accessed asynchronously, and n bit I/O buses for transferring data among the cell arrays. In the DRAM, the banks are divided into m blocks, the n-bit I/O buses located between adjacent banks, is used for time sharing between adjacent banks in common, the n bit I/O buses, used for time sharing between adjacent banks in common, are grouped into n/m-bit I/O buses, every n/m bits for each block of m blocks of bank, and in each block in each bank, data input/output are carried out between the n/m-bit I/O buses and data bus lines in each block. A synchronous DRAM includes a first and second internal clock systems for controlling a burst data transfer in which a string of burst data being transferred in synchronism with an external clock signal, when one of the internal clock systems is driven, the burst data transfer is commenced immediately by the selected internal clock system.

93. 发明授权

US6014335A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US6014335A
公开(公告)日：2000-01-11
申请号：US326948
申请日：1999-06-07
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C29/04 , G11C7/00 , G11C11/401 , G11C11/407 , G11C29/00
CPC分类号： G11C29/785 , G11C29/808 , G11C29/846
摘要： It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a multi-bit memory capable of simultaneously exchanging a plurality of data upon reception of an address, spare DQ lines (15c) commonly used for each I/O, a spare sense amplifier circuit (13c), a spare column switch (14c), a fuse box (20) for storing the address of a DQ line in which a failure has occurred, and fuse circuits (21-1, 21-2, . . . ) for storing an I/O to which the failure-DQ line belongs are arranged to remedy the failure for each I/O. Since only a memory cell belonging to one I/O where a failure has occurred is replaced, unnecessary replacement is not executed, and the memory cell can be efficiently remedied even for a larger number of bits.
摘要翻译：本发明的目的是提供一种半导体存储器件，其中即使对于较大数量的位也可有效地修复故障。在能够在接收到地址时同时交换多个数据的多位存储器中，通常用于每个I / O的备用DQ线（15c），备用读出放大器电路（13c），备用列开关（14c），用于存储其中发生故障的DQ线的地址的保险丝盒（20）和用于存储故障DQ的I / O的熔丝电路（21-1,21-2 ...）排列的行被排列以补救每个I / O的故障。由于只有属于发生故障的一个I / O的存储单元被替换，所以不执行不必要的替换，并且即使对于较大数量的位也能够有效地补救存储单元。

94. 发明授权

US5978300A Semiconductor memory having an overlaid bus structure 失效
公开(公告)号：US5978300A
公开(公告)日：1999-11-02
申请号：US814979
申请日：1997-03-11
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C5/02 , G11C7/10 , G11C8/00
CPC分类号： G11C5/025 , G11C7/10
摘要： A plurality of sense amplifiers are provided between a plurality of memory cell arrays having a plurality of memory cells. These sense amplifiers are connected to bit lines of the respective memory cell arrays by array selection switches. Each of the sense amplifiers is connected to data lines by column switches. An array control portion is provided at each of the memory cell arrays. This array control portion selectively controls the array selection switches and column switches to transmit the data in an arbitrary memory cell in a memory cell array to the data lines through the sense amplifier.

95. 发明授权

US5796660A Memory device and serial-parallel data transform circuit 失效
公开(公告)号：US5796660A
公开(公告)日：1998-08-18
申请号：US815417
申请日：1997-03-11
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/401 , G11C7/10 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/103 , G11C11/4096 , G11C7/1006 , G11C7/1078
摘要： In DRAM, a part of data in a row are rewritten at high speed. The memory device comprises dynamic type cell blocks 11; sense amplifiers 3 for sensing data of the cell blocks 11; latches 2 for storing data; data transfer gates for transferring data between the sense amplifiers 3 and the latches 2; and byte write mask circuit blocks 1 for controlling only the data transfer gates corresponding to only the latches 2 in which data have been written, to transfer data to the sense amplifiers 3. The byte write mask circuit block 1 opens only the transfer gates corresponding to the latches 2 to which data are written and further transfer data from the latches 2 to the sense amplifiers 3. Therefore, when data are required to be written in the cell blocks 11, since only the necessary data are written in the latches 2, it is possible to eliminate wasteful data write to the latches 2, thus enabling a high speed data transfer to the cell blocks 11.

96. 发明授权

US5740122A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5740122A
公开(公告)日：1998-04-14
申请号：US779902
申请日：1997-01-07
申请人： Haruki Toda , Shozo Saito , Kaoru Tokushige
发明人： Haruki Toda , Shozo Saito , Kaoru Tokushige
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/04 , G11C11/407 , G11C11/41 , G11C11/413 , H01L27/10
CPC分类号： G11C7/1072 , G11C7/1018 , G11C7/22
摘要： A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix: a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.
摘要翻译：半导体存储器件包括存储单元组，该存储单元组包括以矩阵形式排列的多个存储单元：指定电路，用于根据存储器单元中的连续地址寻址顺序存储单元，并将其输入到激活状态; 用于对由指定电路指定的连续存储单元进行数据读出/写入操作（数据I / O操作）的数据输入/输出（I / O）电路，该控制基于读出/ 从外部部分提供的写入信号; 用于对从外部提供的基本时钟信号的周期数进行计数的计数器电路; 以及控制器，用于接收从外部部分提供的至少一个或多个指定信号，用于每个指定信号输出用于指定特定周期的控制信号作为开始周期，以对基本时钟信号的周期数进行计数，并且指示计数器电路基于控制信号对基本时钟信号的计数数进行计数，并且用于控制由指定电路执行的指定操作和数据I / O电路的数据I / O操作，使得控制存储单元组的存储器访问操作。

97. 发明授权

US5579275A Video memory system 失效
标题翻译：视频内存系统
公开(公告)号：US5579275A
公开(公告)日：1996-11-26
申请号：US353675
申请日：1994-12-12
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G06F12/04 , G09G5/393 , G09G5/395 , G11C7/10 , G11C8/00
CPC分类号： G11C7/1075 , G09G5/393 , G09G5/395 , G09G2340/12
摘要： A video memory system includes a RAM for storing fixed image data at partial portions, two SAMs each split into at least first and second portions each for transferring a series of data simultaneously to the RAM, without synchronism with each other, a transferring section for transferring data from/to the second portion of the SAM to/from the RAM, when the first portion of the SAM is being accessed in series, and address designating section for determining a head address for serial access in the first portion of the SAM and a final address at which the serial access in the first portion is shifted to serial access in the second portion of the SAM. When two different image data are displayed simultaneously on a display, as when an inserted picture is required to be displayed on a background, it is possible to arrange the image data at predetermined area of the memory, irrespective of the position of the inserted picture on the display.
摘要翻译：视频存储器系统包括用于在部分部分存储固定图像数据的RAM，每个分割成至少第一和第二部分的两个SAM，用于将一系列数据同时传送到RAM，而不是彼此同步;传送部分，用于传送当SAM的第一部分被串行访问时，SAM的第二部分/从RAM的第二部分的数据，以及用于确定SAM的第一部分中的串行访问的头地址的地址指定部分，以及第一部分中的串行访问在SAM的第二部分中被转移到串行访问的最终地址。当在显示器上同时显示两个不同的图像数据时，当插入的图像需要在背景上显示时，可以将图像数据排列在存储器的预定区域，而不管插入的图像的位置如何显示器。

98. 发明授权

US5251181A Random access memory device and method of controlling same in pipe line page mode 失效
标题翻译：随机存取存储器件及其在管道页面模式下的控制方法
公开(公告)号：US5251181A
公开(公告)日：1993-10-05
申请号：US892820
申请日：1992-06-05
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1039
摘要： A random access memory device is provided with data hold circuits connected midway between a column address write circuit and a column select circuit, between a sense amplifier circuit for amplifying data read from the selected column and a data output circuit, between a write data input circuit and a selected column line, respectively. In data write operation, all the data hold circuits are activated at appropriate timings. In data read operation, all but the data hold circuit connected midway between the column address write circuit and the column select circuit are activatged. In both cases, a data is written to the cell, is outputted in the succeeding cycle after the cycle during which the address data is written. Therefore, data transfer operation is executed in sequence through the routes separated by the data hold circuits, thus enabling the higher speed and more efficient data read and write operation.

99. 发明授权

US5249165A Memory cell array divided type multi-port semiconductor memory device 失效
标题翻译：存储单元阵列分割式多端口半导体存储器件
公开(公告)号：US5249165A
公开(公告)日：1993-09-28
申请号：US846913
申请日：1992-03-06
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/401 , G11C7/10 , G11C11/4096 , G11C11/41
CPC分类号： G11C11/4096 , G11C7/1075
摘要： A memory cell array divided type multi-port memory device having random access circuit and serial access circuit, including: a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being disposed in a column direction at a predetermined pitch, each the cell array section having a plurality of word lines and bit lines, the word lines being connected to the memory cells disposed in a row direction for selection of the connected memory cells, and the bit lines being connected to the memory cells disposed in a column direction for data transfer to and from the selected memory cells; a row decoder for activating a desired one of the word lines; sense amplifier provided for each the bit line for sensing data read out to each the bit line; a RAM port connected to the bit lines via RAM transfer gates; a column decoder for selectively turn on/off the RAM transfer gates; a plurality of data transfer lines each having a data transfer gate at the intermediate position thereof, the data transfer lines being connected to the bit lines and formed on a layer different from layers of the word lines and bit lines; data transfer gate control means for turning on/off a desired one of the data transfer gates; a plurality of serial resisters connected to the data transfer lines; a serial port connected via each serial transfer gate to each the serial register; and a serial decoder for serially turning on/off the serial transfer gates.
摘要翻译：一种具有随机存取电路和串行存取电路的存储单元阵列分割型多端口存储器件，包括：多个单元阵列部分，每个单元阵列部分具有以矩阵形式布置的多个存储单元，多个单元阵列部分设置在列方向为预定间距，每个单元阵列部分具有多个字线和位线，字线连接到沿行方向排列的存储单元，用于选择连接的存储单元，位线为连接到沿列方向设置的存储单元，用于从所选择的存储器单元传送数据; 行解码器，用于激活所需的一条字线; 为每个位线提供读出放大器，用于感测读出到每个位线的数据; 通过RAM传输门连接到位线的RAM端口; 用于选择性地打开/关闭RAM传送门的列解码器; 多个数据传输线各自在其中间位置具有数据传输门，数据传输线连接到位线并形成在与字线和位线的层不同的层上; 数据传送门控制装置，用于打开/关闭期望的数据传送门; 连接到数据传输线的多个串行电阻; 通过每个串行传输门连接到每个串行寄存器的串行端口; 以及用于串行打开/关闭串行传输门的串行解码器。

100. 发明授权

US5051954A Semiconductor memory device 失效
公开(公告)号：US5051954A
公开(公告)日：1991-09-24
申请号：US406420
申请日：1989-09-11
申请人： Haruki Toda , Shigeo Ohshima , Tatsuo Ikawa
发明人： Haruki Toda , Shigeo Ohshima , Tatsuo Ikawa
IPC分类号： G11C11/401 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/10
CPC分类号： G11C11/4097 , G11C11/408 , G11C11/4096
摘要： Memory cells disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by a first gate. One memory cell column in the n memory cell colunns in a selected block is selected by a second gate. One memory cell in a selected memory cell column is selected by a row address. The data in a selected memory cell are stored in a register and output therefrom.

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