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91. 发明授权

US07106620B2 Memory cell having improved read stability 有权
标题翻译：具有改善的读稳定性的存储单元
公开(公告)号：US07106620B2
公开(公告)日：2006-09-12
申请号：US11069018
申请日：2005-02-28
申请人： Leland Chang , Robert H. Dennard , Robert Kevin Montoye
发明人： Leland Chang , Robert H. Dennard , Robert Kevin Montoye
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , H01L27/11 , H01L27/1104
摘要： A memory cell for use in a memory array includes a storage element for storing a logical state of the memory cell, a write circuit and a read circuit. The write circuit is operative to selectively connect a first node of the storage element to at least a first write bit line in the memory array in response to a write signal for selectively writing the logical state of the memory cell. The read circuit includes a substantially high impedance input node connected to the storage element and an output node connectable to a read bit line of the memory array. The read circuit is configured to generate an output signal at the output node which is representative of the logical state of the storage element in response to a read signal applied to the read circuit. The memory cell is configured such that the write circuit is disabled during a read operation of the memory cell so as to substantially isolate the storage element from the first write bit line during the read operation. A strength of at least one transistor device in the storage element is separately optimized relative to a strength of at least one transistor device in the write circuit and/or the read circuit.
摘要翻译：用于存储器阵列的存储单元包括用于存储存储单元的逻辑状态的存储元件，写入电路和读取电路。写入电路用于响应于用于选择性地写入存储器单元的逻辑状态的写入信号，有选择地将存储元件的第一节点连接到存储器阵列中的至少第一写入位线。读取电路包括连接到存储元件的基本上高阻抗的输入节点和可连接到存储器阵列的读取位线的输出节点。读取电路被配置为响应于施加到读取电路的读取信号而在输出节点处产生代表存储元件的逻辑状态的输出信号。存储单元被配置为使得在存储单元的读取操作期间禁止写入电路，以便在读取操作期间基本上将存储元件与第一写入位线隔离。存储元件中的至少一个晶体管器件的强度相对于写入电路和/或读取电路中的至少一个晶体管器件的强度分别优化。

92. 发明授权

US08835997B2 Low extension dose implants in SRAM fabrication 有权
标题翻译： SRAM制造中的低延伸剂量植入物
公开(公告)号：US08835997B2
公开(公告)日：2014-09-16
申请号：US13464267
申请日：2012-05-04
申请人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L27/0207 , H01L27/1104 , H01L29/6659
摘要： A static random access memory fabrication array includes at least one p-type field effect transistor, including a gate stack and isolating spacers forming a gate having a gate length Lgate and an effective gate length, Leff and a source and drain region adjacent the gate stack, wherein the source and drain regions are formed from a low extension dose implant that decreases a difference between Lgate and Leff.
摘要翻译：静态随机存取存储器制造阵列包括至少一个p型场效应晶体管，其包括栅极堆叠和形成具有栅极长度L gate和有效栅极长度的栅极的隔离间隔，Leff以及与栅极堆叠相邻的源极和漏极区域其中源极和漏极区域由低延伸剂量植入物形成，其降低了Lgate和Leff之间的差异。

93. 发明申请

US20140049934A1 SLAB INDUCTOR DEVICE PROVIDING EFFICIENT ON-CHIP SUPPLY VOLTAGE CONVERSION AND REGULATION 有权
标题翻译：提供有效的片上电源电压转换和调节的SLAB电感器器件
公开(公告)号：US20140049934A1
公开(公告)日：2014-02-20
申请号：US13589280
申请日：2012-08-20
申请人： Leland Chang , David Goren , Naigang Wang
发明人： Leland Chang , David Goren , Naigang Wang
IPC分类号： H05K9/00
CPC分类号： H02M3/158 , G06F1/26 , H02M3/155 , H02M3/156
摘要： A voltage conversion circuit such as a buck regulator circuit has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches. The voltage conversion circuit can also include means to reduce or cancel a detrimental effect of other wires on same chip, such as a power grid, that conduct a return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.
摘要翻译：诸如降压调节器电路的电压转换电路具有耦合到电压源的多个开关; 具有长度，宽度和厚度的板式电感器，其中所述扁平电感器耦合在所述多个开关之间，并且在所述多个开关的操作期间负载并承载负载电流。电压转换电路还可以包括用于减少或消除导致回流的同一芯片（例如电网）上的其它导线的有害影响并由此降低该扁平电感器的功能性的装置。在一个实施例中，电线可以进一步远离板式电感器，并且在另一个实施例中，磁性材料可用于屏蔽平板电感器与至少一个这样的干扰导体。

94. 发明授权

US08629705B2 Low voltage signaling 有权
标题翻译：低电压信号
公开(公告)号：US08629705B2
公开(公告)日：2014-01-14
申请号：US12794995
申请日：2010-06-07
申请人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
发明人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
IPC分类号： H03L5/00
CPC分类号： H02M3/07 , H02M2003/072
摘要： A low voltage signaling system for integrated circuits includes a first voltage domain operating at a nominal integrated circuit (IC) power supply voltage (Vdd) swing level at a signal transmitting end of a first chip, a second voltage domain having one or more transmission interconnect lines operating at a reduced voltage swing level with respect to the first voltage domain, and a third voltage domain at a signal receiving end of a second chip, the third voltage domain operating at the Vdd swing level; wherein an input signal originating from the first voltage domain is down converted to operate at the reduced voltage swing level for transmission over the second voltage domain, and wherein the third voltage domain senses the input signal transmitted over the second voltage domain and generates an output signal operating back up at the Vdd swing level.
摘要翻译：用于集成电路的低电压信号系统包括在第一芯片的信号发射端处以标称集成电路（IC）电源电压（Vdd）摆幅电平操作的第一电压域，具有一个或多个传输互连的第二电压域以相对于第一电压域的降低的电压摆动电平工作的线路，以及在第二芯片的信号接收端的第三电压域，以Vdd摆动电平工作的第三电压域; 其中源自所述第一电压域的输入信号被降频转换以在所述降低的电压摆幅电平下工作以在所述第二电压域上传输，并且其中所述第三电压域检测在所述第二电压域上传输的输入信号，并产生输出信号以Vdd摆动水平运行。

95. 发明授权

US08536041B2 Method for fabricating transistor with high-K dielectric sidewall spacer 有权
标题翻译：用于制造具有高K电介质侧壁间隔物的晶体管的方法
公开(公告)号：US08536041B2
公开(公告)日：2013-09-17
申请号：US13559182
申请日：2012-07-26
申请人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L27/01
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823462 , H01L21/823468 , H01L21/823807 , H01L21/823857 , H01L21/823864 , H01L27/1203 , H01L29/4958 , H01L29/517 , H01L29/66772 , H01L29/78654
摘要： A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.
摘要翻译：提供了一种用于制造晶体管的方法。该晶体管包括一个硅层，该硅层包括一个源区和一个漏极区，一个位于源极区和漏极区之间的硅层上的栅极堆叠，以及设置在栅叠层的侧壁上的侧壁隔离层。栅堆叠包括第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。侧壁间隔件包括高介电常数材料并且覆盖至少栅极叠层的第二和第三层的侧壁。还提供了制造这种晶体管的方法。

96. 发明授权

US08493093B1 Time division multiplexed limited switch dynamic logic 失效
公开(公告)号：US08493093B1
公开(公告)日：2013-07-23
申请号：US13494607
申请日：2012-06-12
申请人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
发明人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
IPC分类号： H03K19/00
CPC分类号： H03K19/0963 , H03K19/096
摘要： A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

97. 发明申请

US20130176771A1 8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES 有权
标题翻译：具有外部门极二极管的8晶体管SRAM单元设计
公开(公告)号：US20130176771A1
公开(公告)日：2013-07-11
申请号：US13345636
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/40
CPC分类号： G11C16/24 , G11C11/412 , H01L27/0207 , H01L27/1104 , H01L27/1116
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
摘要翻译：一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到通过栅极和写入位之间的串联外部二极管的写入位线的每个通过栅极晶体管的源极或漏极线路阻止从写入位线进入电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

98. 发明申请

US20120259804A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 有权
公开(公告)号：US20120259804A1
公开(公告)日：2012-10-11
申请号：US13083414
申请日：2011-04-08
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

99. 发明申请

US20120187506A1 Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, and Process to Fabricate Same 有权
标题翻译：具有硅侧壁的金属高K晶体管，用于减少寄生电容，以及制造相同的工艺
公开(公告)号：US20120187506A1
公开(公告)日：2012-07-26
申请号：US13432395
申请日：2012-03-28
申请人： Leland Chang , Jeffrey W. Sleight , Isaac Lauer , Renee T. Mo
发明人： Leland Chang , Jeffrey W. Sleight , Isaac Lauer , Renee T. Mo
IPC分类号： H01L29/78
CPC分类号： H01L21/823864 , H01L21/26586 , H01L21/28105 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656
摘要： A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.
摘要翻译：一种方法形成金属高介电常数（MHK）晶体管，包括：提供设置在衬底上的MHK堆叠，MHK堆叠包括第一层高介电常数材料，第二覆盖层和第三覆盖层，选择性地去除仅第二层和第三层，而不去除第一层，以形成MHK栅极结构的直立部分; 在MHK门结构的直立部分的侧壁上形成第一侧壁层; 在所述第一侧壁层的侧壁上形成第二侧壁层; 去除第一层的一部分以形成暴露的表面; 在所述第二侧壁层上并在所述第一层之上形成偏移间隔层，以及在所述第一和第二侧壁层的底部延伸部中形成并且在所述MHK栅极结构的一部分但不是全部直立部分的下方延伸。

100. 发明授权

US08174841B2 Adaptive interconnect structure 失效
标题翻译：自适应互连结构
公开(公告)号：US08174841B2
公开(公告)日：2012-05-08
申请号：US12430416
申请日：2009-04-27
申请人： Leland Chang , Matthew R. Wordeman , Albert M. Young
发明人： Leland Chang , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01R43/00
CPC分类号： H01L25/0657 , H01L23/5252 , H01L23/5256 , H01L24/06 , H01L24/14 , H01L24/16 , H01L25/50 , H01L2224/0401 , H01L2224/05555 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/014 , H01L2924/04953 , H01L2924/00014
摘要： An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.
摘要翻译：半导体结构上的接触焊盘阵列的间距小于用于垂直堆叠半导体结构的接合工艺的覆盖公差的两倍。用于匹配接触针的覆盖变化区域内的一组接触焊盘可以电连接到可编程触点阵列，使得一个可编程触点连接到覆盖变化区域内的每个接触焊盘。一个接触垫可以设置有多个可编程触点。在半导体结构堆叠之后，通过连接或断开可编程触点来容纳接触引脚和接触焊盘之间的接触的可变性。由于接触引脚阵列的间距可能小于接合过程的覆盖变化的两倍，所以垂直堆叠结构中提供了高密度的互连。

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