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91. 发明授权

US07634637B1 Execution of parallel groups of threads with per-instruction serialization 有权
标题翻译：使用每条指令序列化执行并行组线程
公开(公告)号：US07634637B1
公开(公告)日：2009-12-15
申请号：US11305803
申请日：2005-12-16
申请人： John Erik Lindholm , Stuart F. Oberman
发明人： John Erik Lindholm , Stuart F. Oberman
IPC分类号： G06F15/76 , G06F9/00
CPC分类号： G06F9/3851 , G06F9/3853 , G06F9/3879 , G06F9/3885 , G06F9/3887 , G06F9/3891
摘要： In a processor, a SIMD group (a group of threads for which instructions are issued in parallel using single instruction, multiple data instruction issue techniques) is logically divided into two or more “SIMD subsets,” each containing one or more of the threads in the SIMD group. Each SIMD subset is associated with a different instance of a variable state parameter. The processor determines which of the instructions to be executed for the SIMD group rely on the state variable and serializes execution of such instructions so that the instruction is executed separately for each SIMD subset. Instructions that do not rely on the state variable are advantageously not serialized.
摘要翻译：在处理器中，SIMD组（一组线程，其中使用单个指令并行地发出指令，多个数据指令发布技术）在逻辑上被划分为两个或更多个“SIMD子集”，每个包含一个或多个线程 SIMD组。每个SIMD子集与可变状态参数的不同实例相关联。处理器确定要为SIMD组执行的指令中的哪一个依赖于状态变量并串行化这些指令的执行，使得针对每个SIMD子集分别执行该指令。不依赖于状态变量的指令有利地不是序列化的。

92. 发明授权

US07634621B1 Register file allocation 有权
标题翻译：注册文件分配
公开(公告)号：US07634621B1
公开(公告)日：2009-12-15
申请号：US11556677
申请日：2006-11-03
申请人： Brett W. Coon , John Erik Lindholm , Gary Tarolli , Svetoslav D. Tzvetkov , John R. Nickolls , Ming Y. Siu
发明人： Brett W. Coon , John Erik Lindholm , Gary Tarolli , Svetoslav D. Tzvetkov , John R. Nickolls , Ming Y. Siu
IPC分类号： G06F12/00
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F12/0223 , Y02D10/13
摘要： Circuits, methods, and apparatus that provide the die area and power savings of a single-ported memory with the performance advantages of a multiported memory. One example provides register allocation methods for storing data in a multiple-bank register file. In a thin register allocation method, data for a process is stored in a single bank. In this way, different processes use different banks to avoid conflicts. In a fat register allocation method, processes store data in each bank. In this way, if one process uses a large number of registers, those registers are spread among the banks, avoiding a situation where one bank is filled and other processes are forced to share a reduced number of banks. In a hybrid register allocation method, processes store data in more than one bank, but fewer than all the banks. Each of these methods may be combined in varying ways.
摘要翻译：提供具有多端口存储器性能优势的单端口存储器的管芯面积和功率节省的电路，方法和装置。一个示例提供用于将数据存储在多存储器寄存器文件中的寄存器分配方法。在一个薄的寄存器分配方法中，一个进程的数据被存储在一个单独的存储单元中。以这种方式，不同的流程使用不同的银行来避免冲突。在胖寄存器分配方法中，处理将数据存储在每个存储区中。这样一来，如果一个进程使用大量的寄存器，这些寄存器就会在银行之间传播，避免了一个银行被填满的情况，而其他进程被迫分担一个数量减少的银行。在混合寄存器分配方法中，处理将数据存储在多个银行中，但少于所有银行。这些方法中的每一种可以以不同的方式组合。

93. 发明授权

US07543136B1 System and method for managing divergent threads using synchronization tokens and program instructions that include set-synchronization bits 有权
标题翻译：用于使用包括设置同步位的同步令牌和程序指令来管理发散线程的系统和方法
公开(公告)号：US07543136B1
公开(公告)日：2009-06-02
申请号：US11180499
申请日：2005-07-13
申请人： Brett W. Coon , John Erik Lindholm
发明人： Brett W. Coon , John Erik Lindholm
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/30181 , G06F9/322
摘要： One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetching a program instruction, determining that the program instruction is a branch instruction, determining that the program instruction is not a return or break instruction, determining whether the program instruction includes a set-synchronization bit, and updating an active program counter, where the manner in which the active program counter is updated depends on a branch instruction type.
摘要翻译：被配置为管理线程组中的发散线程的计算系统的一个实施例包括配置成存储至少一个令牌和多线程处理单元的堆栈。多线程处理单元被配置为执行获取程序指令，确定程序指令是分支指令，确定程序指令不是返回或中断指令的步骤，确定程序指令是否包括设置同步位并且更新活动程序计数器，其中活动程序计数器的更新方式取决于分支指令类型。

94. 发明授权

US07477255B1 System and method for synchronizing divergent samples in a programmable graphics processing unit 有权
标题翻译：用于在可编程图形处理单元中同步发散样本的系统和方法
公开(公告)号：US07477255B1
公开(公告)日：2009-01-13
申请号：US10823351
申请日：2004-04-12
申请人： John Erik Lindholm , Harold Robert Feldman Zatz , Christian Rouet , Rui M. Bastos
发明人： John Erik Lindholm , Harold Robert Feldman Zatz , Christian Rouet , Rui M. Bastos
IPC分类号： G06F15/00 , G06F7/38
CPC分类号： G06T15/005 , G06F9/322 , G06F9/3851 , G06F9/3887 , G06T2210/52
摘要： A method for synchronizing divergent samples in a programmable graphics processing unit is described. In one embodiment, the method includes the steps of determining that a divergence has occurred and detecting that a first sample of a group of samples has encountered a first synch token. The method also includes the steps of determining whether each of the other samples of the group has encountered a synch token and determining whether the synch token encountered by each of the other samples of the group is the first synch token.
摘要翻译：描述了用于在可编程图形处理单元中同步发散样本的方法。在一个实施例中，该方法包括以下步骤：确定发散已发生，并检测一组样本的第一样本遇到第一同步令牌。该方法还包括以下步骤：确定组中的每个其他样本是否遇到同步令牌，并确定该组中每个其他样本遇到的同步令牌是否是第一同步令牌。

95. 发明申请

US20080109611A1 OPERAND COLLECTOR ARCHITECTURE 有权
标题翻译：操作收集架构
公开(公告)号：US20080109611A1
公开(公告)日：2008-05-08
申请号：US11555649
申请日：2006-11-01
申请人： Samuel Liu , John Erik Lindholm , Ming Y. Siu , Brett W. Coon , Stuart F. Oberman
发明人： Samuel Liu , John Erik Lindholm , Ming Y. Siu , Brett W. Coon , Stuart F. Oberman
IPC分类号： G06F13/00
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/30167 , G06F9/3824 , G06F9/3851 , G06F9/3885
摘要： An apparatus and method for simulating a multi-ported memory using lower port count memories as banks. A collector units gather source operands from the banks as needed to process program instructions. The collector units also gather constants that are used as operands. When all of the source operands needed to process a program instruction have been gathered, a collector unit outputs the source operands to an execution unit while avoiding writeback conflicts to registers specified by the program instruction that may be accessed by other execution units.
摘要翻译：一种使用较低端口计数存储器作为存储体来模拟多端口存储器的装置和方法。收集器单元根据需要从银行收集源操作数，以处理程序指令。收集器单元还收集用作操作数的常量。当收集处理程序指令所需的所有源操作数时，收集器单元将源操作数输出到执行单元，同时避免与由其他执行单元访问的程序指令指定的寄存器的写回冲突。

96. 发明申请

US20080024506A1 A Programmable Graphics Processor For Multithreaded Execution of Programs 有权
标题翻译：用于多线程执行程序的可编程图形处理器
公开(公告)号：US20080024506A1
公开(公告)日：2008-01-31
申请号：US11458633
申请日：2006-07-19
申请人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
发明人： John Erik Lindholm , Brett W. Coon , Stuart F. Oberman , Ming Y. Siu , Matthew P. Gerlach
IPC分类号： G06T1/20
CPC分类号： G06T15/005 , G06F12/0811 , G06F12/0815 , G06F12/0875 , G06T15/10
摘要： A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.
摘要翻译：处理单元包括多个执行流水线，每个执行流水线连接到第一输入部分，用于接收用于像素处理的输入数据和用于接收用于顶点处理的输入数据的第二输入部分和用于存储经处理的像素数据的第一输出部分和用于存储经处理的顶点数据的第二输出部分。经处理的顶点数据被光栅化并扫描转换为用作像素处理的输入数据的像素数据。经处理的像素数据被输出到光栅分析器。

97. 发明授权

US07256796B1 Per-fragment control for writing an output buffer 有权
标题翻译：用于写入输出缓冲区的每个片段控制
公开(公告)号：US07256796B1
公开(公告)日：2007-08-14
申请号：US10910046
申请日：2004-08-03
申请人： Rui M. Bastos , John Erik Lindholm , Matthew N. Papakipos
发明人： Rui M. Bastos , John Erik Lindholm , Matthew N. Papakipos
IPC分类号： G09G5/00
CPC分类号： G06T11/40
摘要： A fragment program may configure a fragment shader to compute a destination position for a fragment, where the destination position is independent of a position computed for the fragment during rasterization of a primitive. The destination position may be computed based on fragment parameters such as color, depth, and transparency. A raster operation unit writes processed fragment data to the destination position. Furthermore, the fragment program may configure the fragment shader to compute a per-fragment stencil operation for use by the raster operation unit during stencil buffering.
摘要翻译：片段程序可以配置片段着色器来计算片段的目的地位置，其中目的地位置独立于在原始光栅化期间为片段计算的位置。可以基于诸如颜色，深度和透明度的片段参数来计算目的地位置。光栅操作单元将处理后的片段数据写入到目标位置。此外，片段程序可以配置片段着色器以计算在片模缓冲期间由光栅操作单元使用的每片段模板操作。

98. 发明授权

US07154507B1 System, method and computer program product for texture shading 有权
标题翻译：用于纹理阴影的系统，方法和计算机程序产品
公开(公告)号：US07154507B1
公开(公告)日：2006-12-26
申请号：US10941198
申请日：2004-09-15
申请人： Henry P. Moreton , John Erik Lindholm , Matthew N. Papakipos , Harold Robert Feldman Zatz
发明人： Henry P. Moreton , John Erik Lindholm , Matthew N. Papakipos , Harold Robert Feldman Zatz
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T15/005
摘要： A system, method and computer program product are provided for texture shading in a hardware graphics processor. Initially, a plurality of texture coordinates is identified. Further, it is determined whether a hardware graphics processor is operating in a texture shader mode. If the hardware graphics processor is operating in the texture shader mode, the texture coordinates are mapped to colors utilizing a plurality of texture shader stages in the hardware graphics processor. If, however, the hardware graphics processor is not operating in the texture shader mode, the texture coordinates are mapped to colors utilizing a conventional graphics application program interface (API) in conjunction with the hardware graphics processor.
摘要翻译：在硬件图形处理器中提供用于纹理着色的系统，方法和计算机程序产品。首先，识别多个纹理坐标。此外，确定硬件图形处理器是否以纹理着色器模式操作。如果硬件图形处理器在纹理着色器模式下操作，则使用硬件图形处理器中的多个纹理着色器级将纹理坐标映射到颜色。然而，如果硬件图形处理器不在纹理着色器模式下操作，则使用与硬件图形处理器结合的常规图形应用程序接口（API）将纹理坐标映射到颜色。

99. 发明授权

US07038685B1 Programmable graphics processor for multithreaded execution of programs 有权
标题翻译：用于多线程执行程序的可编程图形处理器
公开(公告)号：US07038685B1
公开(公告)日：2006-05-02
申请号：US10609967
申请日：2003-06-30
申请人： John Erik Lindholm
发明人： John Erik Lindholm
IPC分类号： G06F15/00 , G06F13/00 , G06F12/02 , G06F9/46 , G06T1/00
CPC分类号： G06T15/005
摘要： A programmable graphics processor for multithreaded execution of program instructions including a thread control unit. The programmable graphics processor is programmed with program instructions for processing primitive, pixel and vertex data. The thread control unit has a thread storage resource including locations allocated to store thread state data associated with samples of two or more types. Sample types include primitive, pixel and vertex. A number of threads allocated to processing a sample type may be dynamically modified.
摘要翻译：一种用于多线程执行包括线程控制单元的程序指令的可编程图形处理器。可编程图形处理器用程序指令编程，用于处理原始，像素和顶点数据。线程控制单元具有包括分配用于存储与两种或多种类型的样本相关联的线程状态数据的位置的线程存储资源。样本类型包括原始，像素和顶点。分配用于处理样本类型的多个线程可以被动态修改。

100. 发明授权

US07009607B2 Method, apparatus and article of manufacture for a transform module in a graphics processor 有权
标题翻译：用于图形处理器中的变换模块的方法，装置和制品
公开(公告)号：US07009607B2
公开(公告)日：2006-03-07
申请号：US09775086
申请日：2001-01-31
申请人： John Erik Lindholm , Simon Moy , David B. Kirk , Paolo E. Sabella
发明人： John Erik Lindholm , Simon Moy , David B. Kirk , Paolo E. Sabella
IPC分类号： G06T17/00
CPC分类号： G06T11/40 , G06T15/005 , G06T15/04 , G06T15/50 , G06T15/503 , G06T15/506
摘要： A method, apparatus and article of manufacture are provided for a transform system for graphics processing as a computer system or on a single integrated circuit. Included is an input buffer adapted for being coupled to a vertex attribute buffer for receiving vertex data therefrom. A multiplication logic unit has a first input coupled to an output of the input buffer. Also provided is an arithmetic logic unit having a first input coupled to an output of the multiplication logic unit. Coupled to an output of the arithmetic logic unit is an input of a register unit. An inverse logic unit is provided including an input coupled to the output of the arithmetic logic unit or the register unit for performing an inverse or an inverse square root operation. Further included is a conversion module coupled between an output of the inverse logic unit and a second input of the multiplication logic unit. In use, the conversion module serves to convert scalar vertex data to vector vertex data. Memory is coupled to the multiplication logic unit and the arithmetic logic unit. The memory has stored therein a plurality of constants and variables for being used in conjunction with the input buffer, the multiplication logic unit, the arithmetic logic unit, the register unit, the inverse logic unit, and the conversion module for processing the vertex data. Finally, an output converter is coupled to the output of the arithmetic logic unit for being coupled to a lighting module to output the processed vertex data thereto.
摘要翻译：提供了一种用于图形处理的变换系统作为计算机系统或单个集成电路的方法，装置和制品。包括适于耦合到顶点属性缓冲器以从其接收顶点数据的输入缓冲器。乘法逻辑单元具有耦合到输入缓冲器的输出的第一输入。还提供了具有耦合到乘法逻辑单元的输出的第一输入的算术逻辑单元。耦合到算术逻辑单元的输出是寄存器单元的输入。提供了一个逆逻辑单元，其包括耦合到算术逻辑单元或寄存器单元的输出的输入，用于执行反或平方根操作。还包括耦合在反逻辑单元的输出和乘法逻辑单元的第二输入之间的转换模块。在使用中，转换模块用于将标量顶点数据转换为向量顶点数据。存储器耦合到乘法逻辑单元和算术逻辑单元。存储器中存储有多个常数和变量，用于与输入缓冲器，乘法逻辑单元，算术逻辑单元，寄存器单元，逆逻辑单元和用于处理顶点数据的转换模块结合使用。最后，输出转换器耦合到算术逻辑单元的输出，用于耦合到照明模块，以将经处理的顶点数据输出到照明模块。

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