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91. 发明申请

US20120241916A1 WAFER EDGE CONDITIONING FOR THINNED WAFERS 有权
标题翻译：用于薄膜波纹的边缘调节
公开(公告)号：US20120241916A1
公开(公告)日：2012-09-27
申请号：US13053803
申请日：2011-03-22
申请人： Timothy Harrison Daubenspeck , Jeffrey P. Gambino , Christopher David Muzzy , Wolfgang Sauter , Timothy Dooling Sullivan
发明人： Timothy Harrison Daubenspeck , Jeffrey P. Gambino , Christopher David Muzzy , Wolfgang Sauter , Timothy Dooling Sullivan
IPC分类号： H01L29/02 , H01L21/302
CPC分类号： H01L21/02021
摘要： The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.
摘要翻译：本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。

92. 发明授权

US08242012B2 Integrated circuit structure incorporating a conductor layer with both top surface and sidewall passivation and a method of forming the integrated circuit structure 有权
标题翻译：集成电路结构包括具有顶表面和侧壁钝化的导体层以及形成集成电路结构的方法
公开(公告)号：US08242012B2
公开(公告)日：2012-08-14
申请号：US12845065
申请日：2010-07-28
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L21/44
CPC分类号： H01L21/76885 , H01L21/76852 , H01L23/3114 , H01L23/525 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/02331 , H01L2224/03462 , H01L2224/0401 , H01L2224/05007 , H01L2224/05008 , H01L2224/05027 , H01L2224/05082 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/13022 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/1305 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要： Disclosed are embodiments of a structure having a metal layer with top surface and sidewall passivation and a method of forming the structure. In one embodiment, a metal layer is electroplated onto a portion of a seed layer at the bottom of a trench. Then, the sidewalls of the metal layer are exposed and, for passivation, a second metal layer is electroplated onto the top surface and sidewalls of the metal layer. In another embodiment, a trench is formed in a dielectric layer. A seed layer is formed over the dielectric layer, lining the trench. A metal layer is electroplated onto the portion of the seed layer within the trench and a second metal layer is electroplated onto the top surface of the metal layer. Thus, in this case, passivation of the top surface and sidewalls of the metal layer is provided by the second metal layer and the dielectric layer, respectively.
摘要翻译：公开了具有具有顶表面和侧壁钝化的金属层的结构的实施例以及形成该结构的方法。在一个实施例中，金属层电镀在沟槽底部的种子层的一部分上。然后，暴露金属层的侧壁，为了钝化，将第二金属层电镀在金属层的顶表面和侧壁上。在另一个实施例中，在电介质层中形成沟槽。在电介质层上形成种子层，衬在沟槽上。将金属层电镀在沟槽内的种子层的部分上，并且将第二金属层电镀到金属层的顶表面上。因此，在这种情况下，金属层的顶表面和侧壁的钝化分别由第二金属层和电介质层提供。

93. 发明授权

US08237279B2 Collar structure around solder balls that connect semiconductor die to semiconductor chip package substrate 有权
标题翻译：将半导体管芯连接到半导体芯片封装衬底的锡球周围的环形结构
公开(公告)号：US08237279B2
公开(公告)日：2012-08-07
申请号：US12879602
申请日：2010-09-10
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L23/48
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02126 , H01L2224/034 , H01L2224/03622 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05572 , H01L2224/05655 , H01L2224/05671 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/13007 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/14 , H01L2924/351 , H01L2924/01074 , H01L2924/01082 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： In one embodiment, a collar structure includes a non-conductive layer that relieves stress around the perimeter of each of the solder balls that connect the semiconductor die to the semiconductor chip package substrate, and another non-conductive layer placed underneath to passivate the entire surface of the die.
摘要翻译：在一个实施例中，套环结构包括非导电层，其将围绕将半导体管芯连接到半导体芯片封装衬底的每个焊球的周边释放应力，以及放置在其下方以钝化整个表面的另一非导电层的死亡。

94. 发明申请

US20120115303A1 METHOD OF FABRICATING DAMASCENE STRUCTURES 有权
标题翻译：制备大分子结构的方法
公开(公告)号：US20120115303A1
公开(公告)日：2012-05-10
申请号：US13354371
申请日：2012-01-20
申请人： Jeffrey P. Gambino , Peter J. Lindgren , Anthony K. Stamper
发明人： Jeffrey P. Gambino , Peter J. Lindgren , Anthony K. Stamper
IPC分类号： H01L21/4763 , H01L21/02
CPC分类号： H01L21/76802 , H01L21/76807 , H01L23/5223 , H01L28/40 , H01L2221/1021 , H01L2221/1063
摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.
摘要翻译：在集成电路中形成导线的方法。所述方法包括在基板上的第一电介质层中形成导线; 在所述导线和所述第一介电层上形成介电阻挡层; 在阻挡层上形成第二电介质层; 在所述第二介电层上形成一个或多个图案化的光致抗蚀剂层; 执行反应离子蚀刻以蚀刻通过第二介电层而不穿过阻挡层的沟槽; 执行第二反应离子蚀刻以将沟槽延伸穿过阻挡层; 并且在执行第二反应离子蚀刻之后，去除一个或多个图案化的光致抗蚀剂层，使用还原等离子体或非氧化等离子体去除最后形成的图案化光致抗蚀剂层。所述方法包括通过与金属 - 绝缘体 - 金属电容器类似的方法形成导线。

95. 发明申请

US20120104600A1 STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE AND PACKAGING THEREOF 审中-公开
标题翻译：结构，半导体结构及制造半导体结构及其包装的方法
公开(公告)号：US20120104600A1
公开(公告)日：2012-05-03
申请号：US13344628
申请日：2012-01-06
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/13 , H01L2224/0401 , H01L2224/05006 , H01L2224/05093 , H01L2224/05567 , H01L2224/05571 , H01L2224/10122 , H01L2224/10126 , H01L2224/13006 , H01L2224/13022 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2224/05552
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括在设计敏感结构和钝化层之间形成的电介质材料。该设计敏感结构包括通过通孔连接器电连接和机械地连接到更高布线层的下布线层。还提供了一种方法和结构。

96. 发明授权

US08120141B2 Method and structure to prevent circuit network charging during fabrication of integrated circuits 失效
标题翻译：在集成电路制造过程中防止电路网络充电的方法和结构
公开(公告)号：US08120141B2
公开(公告)日：2012-02-21
申请号：US11687711
申请日：2007-03-19
申请人： Jeffrey P. Gambino , Kirk D. Peterson
发明人： Jeffrey P. Gambino , Kirk D. Peterson
IPC分类号： H01L21/00 , H01L21/82
CPC分类号： H01L27/1203 , H01L23/5256 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the same or different networks selected from the group consisting of the one or more power distribution networks, the one or more ground distribution networks, the one or more data networks, and combinations thereof.
摘要翻译：集成电路及其制造方法。该集成电路包括：一个或多个配电网络; 一个或多个地面分配网络; 一个或多个数据网络; 并且将相同或不同网络的电力，地线或数据线临时并电连接在一起，从由一个或多个配电网络，一个或多个配电网络，一个或多个配电网络组成的组中选择的相同或不同的网络，更多数据网络及其组合。

97. 发明授权

US08114767B2 Structure, semiconductor structure and method of manufacturing a semiconductor structure and packaging thereof 失效
标题翻译：结构，半导体结构及制造半导体结构的方法及其封装
公开(公告)号：US08114767B2
公开(公告)日：2012-02-14
申请号：US12046616
申请日：2008-03-12
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
IPC分类号： H01L21/4763
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/13 , H01L2224/0401 , H01L2224/05006 , H01L2224/05093 , H01L2224/05567 , H01L2224/05571 , H01L2224/10122 , H01L2224/10126 , H01L2224/13006 , H01L2224/13022 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2224/05552
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括在设计敏感结构和钝化层之间形成的电介质材料。该设计敏感结构包括通过通孔连接器电连接和机械地连接到更高布线层的下布线层。还提供了一种方法和结构。

98. 发明申请

US20120025383A1 INTEGRATED CIRCUIT STRUCTURE INCORPORATING A CONDUCTOR LAYER WITH BOTH TOP SURFACE AND SIDEWALL PASSIVATION AND A METHOD OF FORMING THE INTEGRATED CIRCUIT STRUCTURE 有权
标题翻译：集成电路结构，包含两个顶表面和侧壁钝化的导体层，以及形成集成电路结构的方法
公开(公告)号：US20120025383A1
公开(公告)日：2012-02-02
申请号：US12845065
申请日：2010-07-28
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L21/76885 , H01L21/76852 , H01L23/3114 , H01L23/525 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/02331 , H01L2224/03462 , H01L2224/0401 , H01L2224/05007 , H01L2224/05008 , H01L2224/05027 , H01L2224/05082 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/13022 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/1305 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要： Disclosed are embodiments of a structure having a metal layer with top surface and sidewall passivation and a method of forming the structure. In one embodiment, a metal layer is electroplated onto a portion of a seed layer at the bottom of a trench. Then, the sidewalls of the metal layer are exposed and, for passivation, a second metal layer is electroplated onto the top surface and sidewalls of the metal layer. In another embodiment, a trench is formed in a dielectric layer. A seed layer is formed over the dielectric layer, lining the trench. A metal layer is electroplated onto the portion of the seed layer within the trench and a second metal layer is electroplated onto the top surface of the metal layer. Thus, in this case, passivation of the top surface and sidewalls of the metal layer is provided by the second metal layer and the dielectric layer, respectively.
摘要翻译：公开了具有具有顶表面和侧壁钝化的金属层的结构的实施例以及形成该结构的方法。在一个实施例中，金属层电镀在沟槽底部的种子层的一部分上。然后，暴露金属层的侧壁，为了钝化，将第二金属层电镀在金属层的顶表面和侧壁上。在另一个实施例中，在电介质层中形成沟槽。在电介质层上形成种子层，衬在沟槽上。将金属层电镀在沟槽内的种子层的部分上，并且将第二金属层电镀到金属层的顶表面上。因此，在这种情况下，金属层的顶表面和侧壁的钝化分别由第二金属层和电介质层提供。

99. 发明授权

US08053901B2 Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner 有权
标题翻译：牺牲无机聚合物金属间介质大马士革丝和通孔衬里
公开(公告)号：US08053901B2
公开(公告)日：2011-11-08
申请号：US12917154
申请日：2010-11-01
申请人： Jeffrey P. Gambino , Anthony K. Stamper
发明人： Jeffrey P. Gambino , Anthony K. Stamper
IPC分类号： H01L23/48
CPC分类号： H01L21/02167 , H01L21/02118 , H01L21/02126 , H01L21/02164 , H01L21/0217 , H01L21/02266 , H01L21/02271 , H01L21/02274 , H01L21/312 , H01L21/3121 , H01L21/3122 , H01L21/3148 , H01L21/31612 , H01L21/76807 , H01L21/76811 , H01L21/76813 , H01L21/76831 , H01L21/76835 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2221/1063 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.
摘要翻译：本发明提供一种形成刚性互连结构及其装置的方法，包括以下步骤：提供具有位于下部低k电介质内的第一金属线的下金属布线层; 在下部金属布线层的顶部沉积上部低k电介质; 蚀刻上部低k电介质的至少一部分以向第一金属线提供至少一个通孔; 在所述上部低k电介质的至少一个通路中形成刚性电介质侧壁间隔物; 以及在所述上部低k电介质的至少一部分中形成第二金属线。刚性电介质侧壁间隔物可以包括SiCH，SiC，SiNH，SiN或SiO 2。或者，互连结构的通孔区域可以用包含SiO 2，SiCOH或掺杂的硅酸盐玻璃的机械刚性电介质来加强。

100. 发明申请

US20110227225A1 COPPER ALLOY VIA BOTTOM LINER 失效
标题翻译：铜合金通过底部衬里
公开(公告)号：US20110227225A1
公开(公告)日：2011-09-22
申请号：US13116622
申请日：2011-05-26
申请人： Daniel C. Edelstein , Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Anthony K. Stamper
发明人： Daniel C. Edelstein , Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Anthony K. Stamper
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L23/5226 , H01L2924/0002 , Y10T428/12493 , H01L2924/00
摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.
摘要翻译：通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。

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