专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20070241973A1 Multiband antenna for vehicles 失效
标题翻译：车载多频天线
公开(公告)号：US20070241973A1
公开(公告)日：2007-10-18
申请号：US11515106
申请日：2006-09-01
申请人： Tae-Kwan Cho , Young-Sup Bang , Jin-Ho Kim
发明人： Tae-Kwan Cho , Young-Sup Bang , Jin-Ho Kim
IPC分类号： H01Q1/32
CPC分类号： H01Q1/38 , H01Q1/3275 , H01Q1/42 , H01Q5/357
摘要： Disclosed herein is a multiband antenna for vehicles. The multiband antenna includes a Printed Circuit Board (PCB), at least one radiation unit, and a feeding unit. The PCB is formed within a radome that protects the antenna. The at least one radiation unit is formed on the PCB to be optimized as a Hilbert type meander line composed of a single pattern, and is configured to generate multiband resonant frequencies. The feeding unit is configured to apply signals to the radiation unit.
摘要翻译：这里公开了一种用于车辆的多频带天线。多频带天线包括印刷电路板（PCB），至少一个辐射单元和馈送单元。 PCB在保护天线的天线罩内形成。所述至少一个辐射单元形成在PCB上，以被优化为由单一图案组成的希尔伯特型曲折线，并且被配置为产生多频带谐振频率。馈送单元被配置为将信号施加到辐射单元。

92. 发明申请

US20070139598A1 Vertical alignment mode liquid crystal display device 有权
标题翻译：垂直对准模式液晶显示装置
公开(公告)号：US20070139598A1
公开(公告)日：2007-06-21
申请号：US11637227
申请日：2006-12-11
申请人： Youn-Seung Choi , Jin-Ho Kim
发明人： Youn-Seung Choi , Jin-Ho Kim
IPC分类号： G02F1/1343
CPC分类号： G02F1/1393 , G02F1/133707 , G02F1/134309 , G02F2001/134318
摘要： A VA mode LCD device is disclosed, to improve the viewing-angle properties by isotropically compensating for a viewing angle, in which the VA mode LCD device includes first and second substrates; a plurality of gate and data lines formed on the first substrate, and formed perpendicularly to define a plurality of pixel regions. A thin film transistor is formed in each pixel region of the first substrate. A pixel electrode and a common electrode are formed in each pixel of the respective first and second substrates, wherein the pixel and common electrodes generate an electric field. At least one first slit of a curved-stripe shape, such as a circular-stripe shape, is formed in the pixel electrode of the first substrate. At least one second slit is formed in the common electrode of the second substrate. A liquid crystal layer formed between the first and second substrates.
摘要翻译：公开了VA模式LCD装置，以通过各向同性地补偿视角来改善视角特性，其中VA模式LCD装置包括第一和第二基板; 多个栅极和数据线，形成在第一基板上，并垂直形成以限定多个像素区域。在第一衬底的每个像素区域中形成薄膜晶体管。像素电极和公共电极形成在相应的第一和第二基板的每个像素中，其中像素和公共电极产生电场。在第一基板的像素电极中形成至少一个弯曲条形状的第一狭缝，例如圆形条纹形状。在第二基板的公共电极中形成至少一个第二狭缝。形成在第一和第二基板之间的液晶层。

93. 发明申请

US20060231952A1 BGA semiconductor chip package and mounting structure thereof 失效
标题翻译： BGA半导体芯片封装及其安装结构
公开(公告)号：US20060231952A1
公开(公告)日：2006-10-19
申请号：US11231751
申请日：2005-09-22
申请人： Sang-Young Kim , Jin-Ho Kim , Hee-Jin Park , Young-Hee Song , Tae-Sung Yoon
发明人： Sang-Young Kim , Jin-Ho Kim , Hee-Jin Park , Young-Hee Song , Tae-Sung Yoon
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/49838 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H05K3/303 , H05K3/3436 , H05K3/3452 , H05K2201/094 , H05K2201/09781 , H05K2201/10734 , H05K2201/2036 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In example embodiments of the present invention, a structure of a BGA semiconductor chip package includes a substrate having first and second surfaces, a semiconductor chip having a plurality of bonding pads, and mounted on the first surface of the substrate, and plurality of in/out (I/O) solder balls and dummy solder balls provided on the second surface of the substrate, wherein the I/O solder balls are electrically connected to the semiconductor chip and the dummy solder balls are electrically isolated from the semiconductor chip, and the I/O solder balls and the dummy solder balls have the same ball size and ball pitch and are uniformly provided over the second surface of the substrate.
摘要翻译：在本发明的示例性实施例中，BGA半导体芯片封装的结构包括具有第一和第二表面的衬底，具有多个焊盘的半导体芯片，并且安装在衬底的第一表面上，以及多个入/ （I / O）焊球和设置在基板的第二表面上的虚拟焊球，其中I / O焊球电连接到半导体芯片，并且虚拟焊球与半导体芯片电隔离，并且 I / O焊球和虚拟焊球具有相同的球尺寸和球间距，并均匀地设置在基板的第二表面上。

94. 发明授权

US07112831B2 Ternary content addressable memory cell 有权
标题翻译：三进制内容可寻址存储单元
公开(公告)号：US07112831B2
公开(公告)日：2006-09-26
申请号：US10841775
申请日：2004-05-06
申请人： Jin-Ho Kim , Jong-Mil Youn , Bong-Hyun Choi
发明人： Jin-Ho Kim , Jong-Mil Youn , Bong-Hyun Choi
IPC分类号： H01L27/10 , H01L29/7694 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11 , G11C15/04 , H01L27/105 , H01L27/1052 , H01L27/1104 , Y10S257/903
摘要： Ternary CAM cells are provided. The ternary CAM cell includes a pair of half cells. Each of the half cells includes an isolation layer formed at a predetermined region of a semiconductor substrate to define a match cell active region. A search gate electrode and a node gate electrode are placed to cross over the match cell active region. A match line is electrically connected to the match cell active region, which is adjacent to the node gate electrode and is located opposite the search gate electrode. An SRAM cell is provided at the semiconductor substrate adjacent to the match cell active region. The node gate electrode is electrically connected to one of a pair of storage nodes of the SRAM cell.
摘要翻译：提供三元CAM单元。三元CAM单元包括一对半单元。每个半单元包括形成在半导体衬底的预定区域处以限定匹配单元有源区的隔离层。搜索栅电极和节点栅电极被放置成跨越匹配单元有源区。匹配线电连接到与节点栅电极相邻并且与搜索栅电极相对的匹配单元有源区。 SRAM单元设置在与匹配单元有源区相邻的半导体衬底处。节点栅极电连接到SRAM单元的一对存储节点之一。

95. 发明申请

US20060211255A1 Use of multiple etching steps to reduce lateral etch undercut 审中-公开
标题翻译：使用多个蚀刻步骤来减少横向蚀刻底切
公开(公告)号：US20060211255A1
公开(公告)日：2006-09-21
申请号：US11432222
申请日：2006-05-10
申请人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
发明人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
IPC分类号： H01L21/302
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11539
摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.
摘要翻译：在集成电路制造中，使用具有侧向分量的蚀刻。例如，蚀刻可以是各向同性的。在层（160）的各向同性蚀刻之前，执行相同层的另一蚀刻。这种其他蚀刻可以是各向异性的。该蚀刻攻击通过各向同性蚀刻形成的与特征相邻的层的部分（160×2）。该部分被各向异性蚀刻完全或部分地去除。然后，各向同性蚀刻掩模（420）被形成为延伸超过经过各向异性蚀刻的部分的位置的特征。如果完全去除该部分，则各向同性蚀刻掩模可以完全密封要在该部分侧面上形成的特征，因此不会发生横向蚀刻。如果该部分仅部分被去除，则横向底切将被阻碍，因为在各向同性蚀刻掩模下的特征的通过将变窄。

96. 发明授权

US07098407B2 Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate 有权
标题翻译：用于球栅阵列（BGA）封装的非阻焊掩模型（NSMD）型布线基板及其制造方法
公开(公告)号：US07098407B2
公开(公告)日：2006-08-29
申请号：US10850864
申请日：2004-05-21
申请人： Jin-Ho Kim , In-Ku Kang , Hee-Kook Choi
发明人： Jin-Ho Kim , In-Ku Kang , Hee-Kook Choi
IPC分类号： H05K1/09
CPC分类号： H05K3/3452 , H01L2224/10 , H05K3/243 , H05K2201/0989 , H05K2201/10734 , H05K2203/0577 , H05K2203/058
摘要： In one embodiment, a pad is formed on a substrate surface. The pad is connected with a connecting pattern. A first mask is formed on the substrate. The first mask has a first opening exposing at least a portion of the pad and a portion of the connecting pattern. A second mask is formed on the first mask. The second mask has a second opening exposing at least a portion of the pad and a portion of the connecting pattern. A boundary surface or sidewall of the first opening is not coplanar with a boundary surface or sidewall of the second opening. Therefore, stresses may be prevented from concentrating on the boundary surface of the first opening, thereby allowing dispersion of the stresses and restraining pattern cracks.
摘要翻译：在一个实施例中，衬垫形成在衬底表面上。垫与连接图案连接。在基板上形成第一掩模。第一掩模具有暴露焊盘的至少一部分和连接图案的一部分的第一开口。在第一掩模上形成第二掩模。第二掩模具有暴露焊盘的至少一部分和连接图案的一部分的第二开口。第一开口的边界面或侧壁不与第二开口的边界面或侧壁共面。因此，可以防止应力集中在第一开口的边界面上，从而允许应力分散和约束图案裂纹。

97. 发明申请

US20050240989A1 METHOD OF SHARING STATE BETWEEN STATEFUL INSPECTION FIREWALLS ON MEP NETWORK 审中-公开
标题翻译：在环境网络上进行明确的检查措施之间共享状态的方法
公开(公告)号：US20050240989A1
公开(公告)日：2005-10-27
申请号：US10709255
申请日：2004-04-23
申请人： Jin-Ho Kim , Sae-Woong Bahk , Hee-Jo Lee
发明人： Jin-Ho Kim , Sae-Woong Bahk , Hee-Jo Lee
IPC分类号： H04L9/00 , H04L29/06
CPC分类号： H04L63/0254
摘要： The present invention is devised to solve the problem in which a state cannot be kept track of because an outgoing traffic and an incoming traffic pass through different firewalls on a Multiple Entry/Exit Point (MEP) network having a plurality of entry points. In the present invention, firewalls physically remote from each other can share connection information using a modified SYN cookie, so that stateful inspection firewalls physically remote from each other can be used even on the MEP network.
摘要翻译：本发明旨在解决由于出站业务和入局业务通过具有多个入口点的多入/出点（MEP）网络上的不同防火墙而不能跟踪状态的问题。在本发明中，物理上彼此遥远的防火墙可以使用修改的SYN cookie来共享连接信息，使得即使在MEP网络上也可以使用物理上彼此遥远的状态检查防火墙。

98. 发明申请

US20050054186A1 Wire bonding method, semiconductor chip, and semiconductor package 有权
标题翻译：引线接合方法，半导体芯片和半导体封装
公开(公告)号：US20050054186A1
公开(公告)日：2005-03-10
申请号：US10885769
申请日：2004-07-08
申请人： Jin-Ho Kim , In-Ku Kang , Sang-Yeop Lee
发明人： Jin-Ho Kim , In-Ku Kang , Sang-Yeop Lee
IPC分类号： H01L21/60 , H01L21/44 , H01L21/607
CPC分类号： H01L24/85 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/02126 , H01L2224/02166 , H01L2224/05554 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4809 , H01L2224/48095 , H01L2224/48227 , H01L2224/48245 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/48479 , H01L2224/48599 , H01L2224/48699 , H01L2224/78301 , H01L2224/85045 , H01L2224/85051 , H01L2224/85181 , H01L2224/85205 , H01L2224/85951 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15787 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： A method of wire bonding, a semiconductor chip, and a semiconductor package provides stitch-stitch bonds of a wire on a bond pad of a chip as well as on a bond position of a substrate. A ball-stitch bump is formed on an end of the wire extending from a capillary or provided on the bond pad of the chip. A ball-stitch bump is formed on the bond pad of the chip by pressing down the ball of the wire on the bond pad. A ball-stitch stitch bond of the wire is formed on the ball-stitch bump by pressing down the wire on the ball-stitch bump. The capillary is moved from the bond pad to the bond position, while loosening the wire. A stitch bond of the wire is formed on the bond position by pressing down the wire on the bond position, and then separated from the wire within the capillary. The method of wire bonding, a semiconductor chip, and a semiconductor package can reduce or minimize a moving path of the capillary and provide more effective wire bonding.
摘要翻译：引线键合，半导体芯片和半导体封装的方法在芯片的焊盘和基板的接合位置上提供线的针脚结合。在从毛细管延伸或设置在芯片的接合焊盘上的导线的端部上形成球形针迹。通过在接合焊盘上压下导线的球，在芯片的接合焊盘上形成球针凸点。通过按压球形针凸块上的线，在球形针迹上形成线迹的针迹缝合。毛细管从接合垫移动到接合位置，同时松开电线。通过在接合位置压下导线，在接合位置形成线的针脚接合，然后与毛细管内的线分离。引线键合，半导体芯片和半导体封装的方法可以减少或最小化毛细管的移动路径并提供更有效的引线键合。

99. 发明申请

US20050003630A1 Trench isolation without grooving 有权
标题翻译：沟槽隔离无槽
公开(公告)号：US20050003630A1
公开(公告)日：2005-01-06
申请号：US10901948
申请日：2004-07-29
申请人： Hua Ji , Dong Kim , Jin-Ho Kim , Chuck Jang
发明人： Hua Ji , Dong Kim , Jin-Ho Kim , Chuck Jang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229
摘要： A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.
摘要翻译：提供了一种形成没有沟槽氧化物开槽的浅沟槽隔离区的方法和结构。特别地，一种方法包括两步氧化法，其中氧化物衬垫在沟槽的内表面上划线，并且沟槽填充有本体氧化物层，优选使用高密度等离子体化学气相沉积（HDP-CVD）工艺。氧化物衬垫和本体氧化物层被形成为具有相似的蚀刻速率。因此，当在堆叠结构之间蚀刻氧化物衬垫和本体氧化物层时，形成基本平坦且没有凹槽的公共电介质顶表面。

100. 发明授权

US06818489B2 Semiconductor device having LDD-type source/drain regions and fabrication method thereof 有权
标题翻译：具有LDD型源极/漏极区域的半导体器件及其制造方法
公开(公告)号：US06818489B2
公开(公告)日：2004-11-16
申请号：US10121205
申请日：2002-04-11
申请人： Do-Hyung Kim , Jin-Ho Kim , Byung-Jun Hwang
发明人： Do-Hyung Kim , Jin-Ho Kim , Byung-Jun Hwang
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/76801 , H01L21/76832 , H01L21/76837 , H01L21/76895 , H01L21/823425 , H01L29/6659
摘要： A semiconductor device having LDD-type source/drain regions and a method of fabricating the same are provided. The semiconductor device includes at least a pair of gate patterns disposed on a semiconductor substrate and LDD-type source/drain regions disposed at both sides of the gate patterns. The substrate having the gate patterns and the LDD-type source/drain regions is covered with a conformal etch stop layer. The etch stop layer is covered with an interlayer insulating layer. The LDD-type source/drain region is exposed by a contact hole that penetrates the interlayer insulating layer and the etch stop layer. The method of forming the LDD-type source/drain regions and the etch stop layer includes forming low-concentration source/drain regions at both sides of the gate patterns and forming the conformal etch stop layer on the substrate having the low-concentration source/drain regions. Gate spacers are then formed on the sidewalls of the gate patterns. Using the gate patterns and the gate spacers as implantation masks, impurity ions are implanted into the semiconductor substrate to form high-concentration source/drain regions. The spacers are then selectively removed. An interlayer insulating layer is formed on the substrate where the spacers are removed.
摘要翻译：提供具有LDD型源极/漏极区域的半导体器件及其制造方法。半导体器件包括设置在半导体衬底上的至少一对栅极图案和设置在栅极图案两侧的LDD型源极/漏极区域。具有栅极图案和LDD型源极/漏极区域的衬底被保形蚀刻停止层覆盖。蚀刻停止层被层间绝缘层覆盖。 LDD型源极/漏极区域通过穿透层间绝缘层和蚀刻停止层的接触孔露出。形成LDD型源极/漏极区域和蚀刻停止层的方法包括在栅极图案的两侧形成低浓度源极/漏极区域，并在具有低浓度源/漏极区域的衬底上形成保形蚀刻停止层，漏区。然后在栅极图案的侧壁上形成栅极间隔物。使用栅极图案和栅极间隔物作为注入掩模，将杂质离子注入到半导体衬底中以形成高浓度源极/漏极区域。然后选择性地去除间隔物。在基板上形成层间绝缘层，其中隔离物被去除。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式