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91. 发明授权

US09225311B2 Method of manufacturing switchable filters 有权
标题翻译：制造可切换过滤器的方法
公开(公告)号：US09225311B2
公开(公告)日：2015-12-29
申请号：US13401418
申请日：2012-02-21
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： H03H3/02 , H03H3/007 , H03H9/56 , H03H9/10 , H03H9/24 , H03H3/08 , H03H9/02 , G06F17/50 , H03H9/15
CPC分类号： H03H3/007 , G06F17/5063 , H03H3/02 , H03H3/08 , H03H9/02007 , H03H9/02244 , H03H9/02992 , H03H9/1071 , H03H9/2447 , H03H9/2452 , H03H9/2457 , H03H9/2463 , H03H9/54 , H03H9/56 , H03H9/64 , H03H2003/022 , H03H2003/023 , H03H2003/027 , H03H2009/155 , Y10T29/42 , Y10T29/49005 , Y10T29/49155
摘要： Switchable and/or tunable filters, methods of manufacture and design structures are provided. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.
摘要翻译：提供可切换和/或可调滤波器，制造方法和设计结构。形成滤波器的方法包括形成至少一个压电滤波器结构，其包括形成为与至少一个压电基板接触的多个电极。该方法还包括形成包括MEMS光束的微电子机械结构（MEMS），其中，在致动时，MEMS光束将通过交替与压电基板接触的电极或者将电极之间的至少一个压电基板。

92. 发明授权

US08158453B2 Methods of forming silicide strapping in imager transfer gate device 有权
标题翻译：在成像器传输门装置中形成硅化物带的方法
公开(公告)号：US08158453B2
公开(公告)日：2012-04-17
申请号：US12699419
申请日：2010-02-03
申请人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
发明人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
IPC分类号： H01L21/336
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689
摘要： A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.
摘要翻译：具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

93. 发明授权

US07655966B2 High efficiency CMOS image sensor pixel employing dynamic voltage supply 有权
标题翻译：采用动态电压源的高效率CMOS图像传感器像素
公开(公告)号：US07655966B2
公开(公告)日：2010-02-02
申请号：US12050967
申请日：2008-03-19
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
IPC分类号： H04N3/14
CPC分类号： H04N5/361 , G06F17/5063 , H04N5/359 , H04N5/3745
摘要： A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.
摘要翻译：提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

94. 发明授权

US09054671B2 Tunable filter structures and design structures 有权
标题翻译：可调滤波器结构和设计结构
公开(公告)号：US09054671B2
公开(公告)日：2015-06-09
申请号：US13292729
申请日：2011-11-09
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Mark D. Jaffe , Robert K. Leidy , Anthony K. Stamper
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Mark D. Jaffe , Robert K. Leidy , Anthony K. Stamper
IPC分类号： H03H9/00 , H03H9/17 , H03H9/56 , H03H9/05 , H01L41/00 , H03H9/02
CPC分类号： H03H9/545 , H03H9/0547 , H03H9/171 , H03H9/173 , H03H9/56 , H03H2009/02204 , Y10T29/42
摘要： Tunable filter structures, methods of manufacture and design structures are disclosed. The method of forming a filter structure includes forming a piezoelectric resonance filter over a cavity structure. The forming of the piezoelectric resonance filter includes: forming an upper electrode on one side of a piezoelectric material; and forming a lower electrode on an opposing side of the piezoelectric material. The method further includes forming a micro-electro-mechanical structure (MEMS) cantilever beam at a location in which, upon actuation, makes contact with the piezoelectric resonance filter.
摘要翻译：公开了可调谐滤波器结构，制造方法和设计结构。形成滤波器结构的方法包括在空腔结构上形成压电谐振滤波器。压电谐振滤波器的形成包括：在压电材料的一侧上形成上电极; 以及在所述压电材料的相对侧上形成下电极。该方法还包括在致动时与压电谐振滤波器接触的位置处形成微机电结构（MEMS）悬臂梁。

95. 发明申请

US20100084690A1 CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 有权
标题翻译：具有增强电容的CMOS IMAGER光电二极管
公开(公告)号：US20100084690A1
公开(公告)日：2010-04-08
申请号：US12634898
申请日：2009-12-10
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Dale J. Pearson , Dennis L. Rogers
IPC分类号： H01L27/148 , H01L31/18
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14689 , H01L31/035281
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.
摘要翻译：一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间且形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离，基材表面。在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于在衬底表面形成的掺杂层的下方。

96. 发明授权

US07675097B2 Silicide strapping in imager transfer gate device 有权
标题翻译：成像器中的硅化物贴带传输门装置
公开(公告)号：US07675097B2
公开(公告)日：2010-03-09
申请号：US11565801
申请日：2006-12-01
申请人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
发明人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
IPC分类号： H01L27/146
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689
摘要： A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.
摘要翻译：具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

97. 发明授权

US07491561B2 Pixel sensor having doped isolation structure sidewall 有权
标题翻译：具有掺杂隔离结构侧壁的像素传感器
公开(公告)号：US07491561B2
公开(公告)日：2009-02-17
申请号：US11563531
申请日：2006-11-27
申请人： James W. Adkisson , Mark D. Jaffe , Robert K. Leidy
发明人： James W. Adkisson , Mark D. Jaffe , Robert K. Leidy
IPC分类号： H01L21/84
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14683
摘要： A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the trench are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material.
摘要翻译：形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成沟槽隔离结构。沟槽隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散工艺，由此在退火期间，存在于沿着沟槽中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来执行。

98. 发明申请

US20080128767A1 SILICIDE STRAPPING IN IMAGER TRANSFER GATE DEVICE 有权
标题翻译：图像转印门装置中的硅胶缠绕
公开(公告)号：US20080128767A1
公开(公告)日：2008-06-05
申请号：US11565801
申请日：2006-12-01
申请人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
发明人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689
摘要： A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.
摘要翻译：具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

99. 发明授权

US07098067B2 Masked sidewall implant for image sensor 有权
标题翻译：用于图像传感器的蒙版侧植入物
公开(公告)号：US07098067B2
公开(公告)日：2006-08-29
申请号：US10905043
申请日：2004-12-13
申请人： James W. Adkisson , Mark D. Jaffe , Arthur P. Johnson , Robert K. Leidy , Jeffrey C. Maling
发明人： James W. Adkisson , Mark D. Jaffe , Arthur P. Johnson , Robert K. Leidy , Jeffrey C. Maling
IPC分类号： H01L21/00
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14687 , H01L27/14689
摘要： A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a dopant region comprising material of the first conductivity type formed along a sidewall of the isolation region that is adapted to electrically couple the pinning layer to the substrate. The corresponding method facilitates an angled ion implantation of dopant material in the isolation region sidewall by first fabricating the photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material. To facilitate the angled implant to the sidewall edge past resist block masks, two methods are proposed: 1) a spacer type etch of the imaged photoresist; or, 2) a corner sputter process of the imaged photoresist.
摘要翻译：形成在第一导电类型的衬底上的新型图像传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成沟槽隔离区。该结构包括掺杂区域，该掺杂剂区域包括沿着隔离区域的侧壁形成的第一导电类型的材料，其适于将钉扎层电耦合到衬底。相应的方法通过首先制造光致抗蚀剂层并且通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来促进掺杂剂材料在隔离区域侧壁中的成角度的离子注入。为了促进通过抗蚀剂阻挡掩模的侧壁边缘的成角度注入，提出了两种方法：1）成像光致抗蚀剂的间隔物型蚀刻; 或2）成像光致抗蚀剂的角溅射工艺。

100. 发明申请

US20090180010A1 LOW LAG TRANSFER GATE DEVICE 有权
标题翻译： LOW LAG传输闸门装置
公开(公告)号：US20090180010A1
公开(公告)日：2009-07-16
申请号：US12013826
申请日：2008-01-14
申请人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan
发明人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan
IPC分类号： H04N3/14 , H01L31/18
CPC分类号： H01L31/103 , H04N5/353 , H04N5/374 , H04N5/3745
摘要： A method of forming a CMOS active pixel sensor (APS) cell structure having at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure. Alternately, an intermediate charge storage device and second transfer gate device may be provided which may first temporarily receive charge carriers from the photosensing device, and, upon activating the second transfer gate device in a further timed fashion, read out the charge stored at the intermediate charge storage device for transfer to the second transfer gate device while preventing spillback of charges to the photosensing device. The APS cell structure is further adapted for a global shutter mode of operation, and further comprises a light shield element is further provided to ensure no light reaches the photosensing and charge storage devices during charge transfer operation.
摘要翻译：一种形成具有至少一个传输栅极器件和操作方法的CMOS有源像素传感器（APS）单元结构的方法。第一传输栅极器件包括具有第一导电类型材料的第一掺杂区域和第二导电类型材料的第二掺杂区域的二极或分裂传输栅极导体结构。光敏装置形成在第一掺杂区域附近，用于响应于入射到其上的光而收集电荷载流子，并且第二导电类型材料的扩散区域形成在与传输栅极器件的第二掺杂区域相邻的衬底表面处或下方用于接收从光敏装置转移的电荷，同时防止在针对二极或分离转移栅极导体结构的定时电压偏压时对光敏装置的电荷溢出。或者，可以提供中间电荷存储装置和第二传输门装置，其可以首先临时从光敏装置接收电荷载体，并且在以另外的定时方式激活第二传输门装置时，读出存储在中间电荷存储装置，用于传送到第二传输门装置，同时防止电荷向光感器件溢出。 APS单元结构进一步适用于全局快门操作模式，并且进一步包括遮光元件，以在电荷转移操作期间确保没有光到达光敏和电荷存储装置。

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