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91. 发明申请

US20090271795A1 Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor 有权
公开(公告)号：US20090271795A1
公开(公告)日：2009-10-29
申请号：US12380575
申请日：2009-02-27
申请人： Jaroslaw J. Sydir , Chen-Chi Kuo , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
发明人： Jaroslaw J. Sydir , Chen-Chi Kuo , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F9/5033
摘要： A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.

92. 发明授权

US07529924B2 Method and apparatus for aligning ciphered data 有权
标题翻译：用于对齐加密数据的方法和装置
公开(公告)号：US07529924B2
公开(公告)日：2009-05-05
申请号：US10749035
申请日：2003-12-30
申请人： Jaroslaw Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
发明人： Jaroslaw Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
IPC分类号： H04L9/00
CPC分类号： H04L63/0485 , H04L63/126
摘要： A data processing device includes a crypto unit having an alignment buffer for providing data to transmit buffer elements of a media switch fabric in multiples of a predetermined number of bytes. Ciphered data for a packet can be split over first and second transmit buffer elements so as to reduce the amount of software intervention.
摘要翻译：数据处理装置包括具有对准缓冲器的加密单元，用于以预定数量的字节的倍数提供数据以传送介质交换结构的缓冲器元件。分组的加密数据可以分割在第一和第二发送缓冲器元件上，以便减少软件干预的量。

93. 发明授权

US07467256B2 Processor having content addressable memory for block-based queue structures 有权
标题翻译：具有内容可寻址存储器的处理器，用于基于块的队列结构
公开(公告)号：US07467256B2
公开(公告)日：2008-12-16
申请号：US11027601
申请日：2004-12-28
申请人： Sanjeev Jain , Gilbert M. Wolrich , Debra Bernstein
发明人： Sanjeev Jain , Gilbert M. Wolrich , Debra Bernstein
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L45/7453 , H04L49/90
摘要： Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.
摘要翻译：排队命令信息存储在内容可寻址存储器（CAM）中，其中接收到用于第一队列的排队命令，检查CAM以确定是否存在用于第一队列的命令，并且如果发现第一队列的命令是在多个CAM条目中，信息被存储在所接收的命令的链表中。

94. 发明授权

US07441245B2 Phasing for a multi-threaded network processor 有权
标题翻译：分阶段的多线程网络处理器
公开(公告)号：US07441245B2
公开(公告)日：2008-10-21
申请号：US10642053
申请日：2003-08-14
申请人： Donald F. Hooper , Mark Rosenbluth , Debra Bernstein , Michael F. Fallon , Sanjeev Jain , Gilbert M. Wolrich
发明人： Donald F. Hooper , Mark Rosenbluth , Debra Bernstein , Michael F. Fallon , Sanjeev Jain , Gilbert M. Wolrich
IPC分类号： G06F9/46 , G06F9/30 , G06F9/00
CPC分类号： G06F9/5038 , G06F2209/5018 , H04L69/12
摘要： A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.
摘要翻译：一种用于将数据单元与多线程处理器的线程相关联以用于处理的方法和装置，并且使得每个线程能够在线程执行周期期间对至少两个数据单元执行处理。线程执行周期在各个阶段之间分割，线程处理的每个数据单元都由不同的相位进行处理。

95. 发明授权

US07418543B2 Processor having content addressable memory with command ordering 有权
标题翻译：具有内容可寻址存储器的处理器，具有命令排序
公开(公告)号：US07418543B2
公开(公告)日：2008-08-26
申请号：US11018591
申请日：2004-12-21
申请人： Sanjeev Jain , Gilbert M. Wolrich , Debra Bernstein
发明人： Sanjeev Jain , Gilbert M. Wolrich , Debra Bernstein
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： A content addressable memory (CAM) includes a linked list structure for a pending queue to order memory commands for maximizing memory channel bandwidth by minimizing read/write stalls due to read-modify-write commands.
摘要翻译：内容可寻址存储器（CAM）包括用于等待队列的链接列表结构，以通过最小化由于读取 - 修改 - 写入命令引起的读取/写入停顿来排序存储器命令以最大化存储器通道带宽。

96. 发明申请

US20080069337A1 SYSTEM AND METHOD FOR MULTI-PRECISION DIVISION 失效
标题翻译：多精度部分的系统和方法
公开(公告)号：US20080069337A1
公开(公告)日：2008-03-20
申请号：US11469243
申请日：2006-08-31
申请人： Vinodh Gopal , Matt Bace , Gunnar Gaubatz , Gilbert M. Wolrich
发明人： Vinodh Gopal , Matt Bace , Gunnar Gaubatz , Gilbert M. Wolrich
IPC分类号： H04L9/28 , H04L9/30 , H04L9/00 , G06G7/16 , H04K1/00
CPC分类号： G06F7/535 , G06F2207/3896
摘要： The present disclosure provides a system and method for performing multi-precision division. A method according to one embodiment may include generating a first product by multiplying a modulus having a most significant bit and/or a least significant bit equal to one and a quotient approximation of the modulus. The method may also include generating the 1's complement of the first product, generating a second product by multiplying the 1's complement and the quotient approximation, normalizing and truncating the second product to obtain a quotient, and storing the quotient in memory. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行多精度分割的系统和方法。根据一个实施例的方法可以包括通过将具有最高有效位和/或最低有效位的模数乘以等于1的模数和模量的商近似来生成第一乘积。该方法还可以包括生成第一产品的1的补码，通过乘以1的补码和商近似来生成第二乘积，归一化和截断第二乘积以获得商，并将商存储在存储器中。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

97. 发明申请

US20080059865A1 APPARATUS AND METHOD FOR GENERATING A GALOIS-FIELD SYNDROME 失效
标题翻译：用于产生GALOIS-FIELD SYNDROME的装置和方法
公开(公告)号：US20080059865A1
公开(公告)日：2008-03-06
申请号：US11469222
申请日：2006-08-31
申请人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
发明人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
IPC分类号： G11C29/00
CPC分类号： G06F11/1076 , G06F2211/1054 , G06F2211/1057
摘要： The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

98. 发明授权

US07336606B2 Circular link list scheduling 有权
标题翻译：循环链表调度
公开(公告)号：US07336606B2
公开(公告)日：2008-02-26
申请号：US10641324
申请日：2003-08-14
申请人： David Romano , Gilbert M. Wolrich , Donald F. Hooper
发明人： David Romano , Gilbert M. Wolrich , Donald F. Hooper
IPC分类号： G01R31/08
CPC分类号： H04L49/254 , H04L47/50 , H04L47/568
摘要： A scheduling mechanism to control transmission of data units, such as variable size packets or fixed size cells, to ports of a network device such as a switching fabric system. The scheduling mechanism maintains scheduling data structures, including an array storing information for available queues of ports and circular buffers representing nonempty port queues of the available port queues according to classes of service. The scheduling mechanism uses the data structures to make scheduling decisions concerning the scheduling of data units in the nonempty port queues for transmission to the ports.
摘要翻译：控制诸如可变大小分组或固定大小小区之类的数据单元的传输到诸如交换结构系统的网络设备的端口的调度机制。调度机制维护调度数据结构，包括根据服务类别存储可用队列的信息和表示可用端口队列的非空端口队列的循环缓冲区。调度机制使用数据结构来做出关于非空端口队列中的数据单元的调度的调度决定，以传送到端口。

99. 发明申请

US20080022175A1 Program memory having flexible data storage capabilities 审中-公开
标题翻译：具有灵活数据存储功能的程序存储器
公开(公告)号：US20080022175A1
公开(公告)日：2008-01-24
申请号：US11478393
申请日：2006-06-29
申请人： Sanjeev Jain , Mark B. Rosenbluth , Gilbert M. Wolrich , Jose S. Niell
发明人： Sanjeev Jain , Mark B. Rosenbluth , Gilbert M. Wolrich , Jose S. Niell
IPC分类号： G01R31/28
CPC分类号： G06F9/3802 , G06F9/30043 , G06F9/342 , G06F9/3824 , G06F9/3851
摘要： A method according to one embodiment may include performing one or more fetch operations to retrieve one or more instructions from a program memory; scheduling a write instruction to write data from at least one data register into the program memory; and stealing one or more cycles from one or more of the fetch operations to write the data in the at least one data register into the program memory. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的方法可以包括执行一个或多个提取操作以从程序存储器检索一个或多个指令; 调度写指令以将数据从至少一个数据寄存器写入程序存储器; 以及从一个或多个获取操作中窃取一个或多个周期，以将所述至少一个数据寄存器中的数据写入程序存储器。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

100. 发明授权

US6131107A Fast determination of carry inputs from lower order product for radis-8 odd/even multiplier array 有权
标题翻译：快速确定radis-8奇数/偶数乘法器阵列的低阶乘积的进位输入
公开(公告)号：US6131107A
公开(公告)日：2000-10-10
申请号：US208169
申请日：1998-12-09
申请人： Gilbert M. Wolrich , Sribalan Santhanam , Andrew S. Olesin
发明人： Gilbert M. Wolrich , Sribalan Santhanam , Andrew S. Olesin
IPC分类号： G06F7/52
CPC分类号： G06F7/5312 , G06F7/5336 , G06F2207/3884 , G06F7/483 , G06F7/49942 , G06F7/49947 , G06F7/49994
摘要： A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.
摘要翻译：浮点处理器中的乘法器包括一个电路，用于确定乘法器操作数的每一位3次展位重新编码，以及一个实施3次展位重新编码乘法的展位重新编码乘法器阵列。乘法器包括用于确定快速符号的逻辑，用于替换在阵列中移位的位位置以及舍入加法器，以在确定来自展位重新编码乘数的最终结果的同时提供舍入结果。乘法器还包括一个电路，用于确定对较低阶乘积的最终相乘结果的贡献，并形成整个乘积。

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