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91. 发明授权

US07402856B2 Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same 有权
标题翻译：具有隔离元件以减轻边缘效应的非平面微电子器件及其制造方法
公开(公告)号：US07402856B2
公开(公告)日：2008-07-22
申请号：US11299102
申请日：2005-12-09
申请人： Justin K. Brask , Jack T. Kavalieros , Brian S. Doyle , Robert S. Chau
发明人： Justin K. Brask , Jack T. Kavalieros , Brian S. Doyle , Robert S. Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.
摘要翻译：非平面微电子器件，制造器件的方法以及包括该器件的系统。所述非平面微电子器件包括：衬底主体，其包括衬底基座和鳍片，所述鳍片限定其顶部区域处的器件部分; 栅极电介质层，其在所述鳍片的两个横向相对的侧壁上以预定高度延伸，所述预定高度对应于所述器件部分的高度; 在所述衬底主体上的器件隔离层，并且具有至所述器件部分的下限的厚度; 器件隔离层上的栅电极，并进一步在栅介质层上延伸; 隔离元件，其在所述鳍片的两个横向相对的侧壁上延伸到所述栅极电介质层的下限，所述隔离元件适于减小所述栅电极与所述鳍片延伸到所述器件部分下方的区域之间的任何条纹电容。

92. 发明授权

US06953719B2 Integrating n-type and p-type metal gate transistors 有权
公开(公告)号：US06953719B2
公开(公告)日：2005-10-11
申请号：US10851360
申请日：2004-05-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

93. 发明授权

US08169027B2 Substrate band gap engineered multi-gate pMOS devices 有权
标题翻译：基板带隙工程多栅极pMOS器件
公开(公告)号：US08169027B2
公开(公告)日：2012-05-01
申请号：US12757917
申请日：2010-04-09
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
IPC分类号： H01L29/66
CPC分类号： H01L29/78687 , H01L29/66545 , H01L29/785 , H01L29/78609
摘要： A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
摘要翻译：多栅极晶体管和形成多栅极晶体管的方法，所述多栅极晶体管包括具有上部和下部的鳍。所述上部具有第一带隙，并且所述下部具有与所述第一带隙和所述第二带隙的第二带隙，所述第二带隙被设计成阻止电流从所述上部向下部流动。多栅极晶体管还包括具有与所述上部和所述下部电耦合的侧壁的栅极结构和位于鳍下方的衬底。

94. 发明授权

US07858481B2 Method for fabricating transistor with thinned channel 有权
标题翻译：用稀疏通道制造晶体管的方法
公开(公告)号：US07858481B2
公开(公告)日：2010-12-28
申请号：US11154138
申请日：2005-06-15
申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
摘要翻译：描述了制造具有减薄沟道区的MOS晶体管的方法。在去除虚拟栅极之后蚀刻沟道区。源极和漏极区域具有相对较低的电阻。

95. 发明授权

US07821061B2 Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications 有权
标题翻译：用于逻辑和多级存储器应用的硅锗和锗多重和纳米线结构
公开(公告)号：US07821061B2
公开(公告)日：2010-10-26
申请号：US11729565
申请日：2007-03-29
申请人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/00
CPC分类号： H01L21/02381 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/31658 , H01L21/76283 , H01L21/823807 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/165 , H01L29/42324 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要翻译：一种提供晶体管或存储单元结构的方法。该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。

96. 发明申请

US20100193840A1 SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES 有权
标题翻译：基板带隙工程多栅极PMOS器件
公开(公告)号：US20100193840A1
公开(公告)日：2010-08-05
申请号：US12757917
申请日：2010-04-09
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
IPC分类号： H01L27/088
CPC分类号： H01L29/78687 , H01L29/66545 , H01L29/785 , H01L29/78609
摘要： A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
摘要翻译：多栅极晶体管和形成多栅极晶体管的方法，所述多栅极晶体管包括具有上部和下部的鳍。所述上部具有第一带隙，并且所述下部具有与所述第一带隙和所述第二带隙的第二带隙，所述第二带隙被设计成阻止电流从所述上部向下部流动。多栅极晶体管还包括具有与所述上部和所述下部电耦合的侧壁的栅极结构和位于鳍下方的衬底。

97. 发明申请

US20090140341A1 INDEPENDENT N-TIPS FOR MULTI-GATE TRANSISTORS 有权
标题翻译：独立的N-TIPS多门控晶体管
公开(公告)号：US20090140341A1
公开(公告)日：2009-06-04
申请号：US11948414
申请日：2007-11-30
申请人： Ravi Pillarisetty , Suman Datta , Jack T. Kavalieros , Brian S. Doyle
发明人： Ravi Pillarisetty , Suman Datta , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11 , H01L29/785
摘要： Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device.
摘要翻译：通常描述多栅极晶体管的独立n尖端。在一个示例中，设备包括半导体鳍片，与半导体鳍片耦合的一个或多个多栅极下拉（PD）器件，所述一个或多个PD器件在与半导体鳍片材料相邻的半导体鳍片材料中具有n端掺杂剂浓度一个或多个PD器件，以及与半导体鳍片耦合的一个或多个多栅极通过栅极（PG）器件，所述一个或多个PG器件在与所述一个或多个PG相邻的半导体鳍片材料中具有n尖端掺杂剂浓度器件，其中PG器件的n尖掺杂剂浓度低于PD器件的n尖掺杂剂浓度。

98. 发明授权

US07485536B2 Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers 有权
标题翻译：通过原子层外延原位δ掺杂掺杂剂扩散阻挡层的突变结形成
公开(公告)号：US07485536B2
公开(公告)日：2009-02-03
申请号：US11326178
申请日：2005-12-30
申请人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
发明人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
IPC分类号： H01L21/335
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要： A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.
摘要翻译：一种方法，包括在衬底中的源区和漏区之间形成沟道区，所述沟道区包括第一掺杂物分布; 以及在所述沟道区和所述衬底的阱之间形成阻挡层，所述阻挡层包括不同于所述第一掺杂剂分布的第二掺杂剂分布。一种在基板上包括栅电极的装置; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及在衬底的阱和沟道区之间的阻挡层，阻挡层包括不同于沟道区的掺杂物分布并且不同于阱的掺杂剂分布的掺杂剂分布。一种包括包括微处理器的计算设备的系统，所述微处理器包括形成在衬底中的多个晶体管器件，所述多个晶体管器件中的每一个在所述衬底上包括栅电极; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及衬底的阱和沟道区之间的阻挡层。

99. 发明申请

US20080157225A1 SRAM and logic transistors with variable height multi-gate transistor architecture 审中-公开
标题翻译：具有可变高度多栅极晶体管结构的SRAM和逻辑晶体管
公开(公告)号：US20080157225A1
公开(公告)日：2008-07-03
申请号：US11648521
申请日：2006-12-29
申请人： Suman Datta , Brian S. Doyle , Jack T. Kavalieros , Yih Wang
发明人： Suman Datta , Brian S. Doyle , Jack T. Kavalieros , Yih Wang
IPC分类号： H01L21/336 , H01L29/768
CPC分类号： H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/66795 , H01L29/7851
摘要： Multi-gate transistors having different channel widths formed on non-planar semiconductor bodies have different sidewall heights and method of manufacturing the same. In an embodiment, a multi-gate SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a multi-gate logic transistor to improve performance of SRAM and logic transistors formed on the same substrate. In another embodiment, to reduce cell area, a first SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a second multi-gate SRAM transistor.
摘要翻译：形成在非平面半导体主体上的具有不同沟道宽度的多栅极晶体管具有不同的侧壁高度及其制造方法。在一个实施例中，多栅极SRAM晶体管形成在具有比用于多栅极逻辑晶体管的非平面半导体主体更大的侧壁高度的非平面半导体主体上，以改善在栅极上形成的SRAM和逻辑晶体管的性能相同的底物。在另一个实施例中，为了减小单元面积，第一SRAM晶体管形成在具有比用于第二多栅极SRAM晶体管的非平面半导体主体更大的侧壁高度的非平面半导体本体上。

100. 发明授权

US07235809B2 Semiconductor channel on insulator structure 有权
标题翻译：半导体通道绝缘体结构
公开(公告)号：US07235809B2
公开(公告)日：2007-06-26
申请号：US11292911
申请日：2005-12-01
申请人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L29/06
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02466 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L21/02664 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L29/66742 , H01L29/78603 , H01L29/78648 , H01L29/78681
摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.
摘要翻译：一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

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