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91. 发明申请

US20140308806A1 TAPERED FIN FIELD EFFECT TRANSISTOR 有权
标题翻译：锥形场效应晶体管
公开(公告)号：US20140308806A1
公开(公告)日：2014-10-16
申请号：US14021165
申请日：2013-09-09
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Michael A. Guillorn , Chung-Hsun Lin , Ryan M. Martin , Jeffrey W. Sleight
IPC分类号： H01L21/306
CPC分类号： H01L29/7853 , H01L21/306 , H01L21/3065 , H01L29/66795 , Y02P80/30
摘要： A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.
摘要翻译：可以使用锥形鳍式场效应晶体管来提供通道的增强的静电控制。在绝缘体层上形成具有基本上垂直的侧壁表面的半导体鳍片和介电鳍片盖的叠层。半导体鳍片的侧壁表面被具有锥形厚度轮廓的介电翅片帽的蚀刻残余物材料钝化，使得蚀刻残余物质的厚度随着与介电翅片盖的距离而减小。使用包括各向同性蚀刻部件的蚀刻来去除蚀刻残留物并且物理地暴露半导体鳍片的侧壁的下部。蚀刻横向蚀刻半导体鳍片并在底部形成锥形区域。半导体鳍片的底部的减小的横向宽度允许更好地控制鳍状场效应晶体管的沟道。

92. 发明申请

US20140306286A1 TAPERED FIN FIELD EFFECT TRANSISTOR 审中-公开
公开(公告)号：US20140306286A1
公开(公告)日：2014-10-16
申请号：US13860136
申请日：2013-04-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Josephine B. Chang , Michael A. Guillorn , Chung-Hsun Lin , Ryan M. Martin , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7853 , H01L21/306 , H01L21/3065 , H01L29/66795 , Y02P80/30
摘要： A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

93. 发明申请

US20140264286A1 SUSPENDED SUPERCONDUCTING QUBITS 有权
标题翻译：悬挂超级QUBITS
公开(公告)号：US20140264286A1
公开(公告)日：2014-09-18
申请号：US13834291
申请日：2013-03-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Josephine B. Chang , George A. Keefe , Chad T. Rigetti , Mary E. Rothwell
IPC分类号： H01L29/66 , G06N99/00 , H01L21/304
CPC分类号： H01L39/2493 , G06N99/002 , H01L21/304 , H01L27/18 , H01L39/045 , H01L39/223
摘要： A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.
摘要翻译：量子比特系统包括衬底层，悬垂在衬底层上的量子位电路以及设置在量子位电路和衬底层之间的精细结构。

94. 发明申请

US20140217508A1 Diode Structure and Method for FINFET Technologies 有权
公开(公告)号：US20140217508A1
公开(公告)日：2014-08-07
申请号：US13967888
申请日：2013-08-15
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/12
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66545 , H01L29/785 , H01L29/861
摘要： A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

95. 发明申请

US20140217364A1 Diode Structure and Method for Wire-Last Nanomesh Technologies 有权
标题翻译：最终纳米技术的二极管结构和方法
公开(公告)号：US20140217364A1
公开(公告)日：2014-08-07
申请号：US13971974
申请日：2013-08-21
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleights
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , B82Y10/00 , B82Y40/00 , B82Y99/00 , H01L27/0629 , H01L29/0673 , H01L29/16 , H01L29/42392 , H01L29/66136 , H01L29/66439 , H01L29/66477 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L29/861 , Y10S977/762 , Y10S977/938
摘要： In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.
摘要翻译：一方面，一种制造电子设备的方法包括以下步骤。在SOI晶片上的堆叠中形成交替的器件和牺牲层系列。将纳米线棒蚀刻到器件/牺牲层中，使得堆叠的第一部分中的每个器件层和堆叠的第二部分中的每个器件层具有源极区，漏极区和多个纳米线通道连接源极区域和漏极区域。从纳米线条之间移除牺牲层。选择性地形成围绕堆叠的第一部分中的纳米线通道的共形栅极介电层，其用作纳米级FET晶体管的沟道区。在堆叠的第一和第二部分中围绕纳米线通道形成栅极。

96. 发明授权

US08796742B1 Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain 有权
标题翻译：具有上限生长的源极和漏极的非替代栅极纳米场效应晶体管
公开(公告)号：US08796742B1
公开(公告)日：2014-08-05
申请号：US14022735
申请日：2013-09-10
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Paul Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/745 , H01L29/74 , H01L21/336
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y40/00 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.
摘要翻译：将两个不同的半导体材料的交替堆叠图案化以包括两个焊盘区域和纳米线区域。对另一半导体材料的半导体材料进行横向蚀刻选择性以形成包括悬浮半导体纳米线的纳米片。在纳米级上形成栅极电介质，栅电极和栅极帽电介质。在栅电极周围形成介电隔离件。使用电介质间隔物和栅极盖电介质作为蚀刻掩模去除两个焊盘区域中的半导体材料和纳米薄膜的物理暴露部分。源极区域和漏极区域从纳米单体的端面外延生长。

97. 发明授权

US08785981B1 Non-replacement gate nanomesh field effect transistor with pad regions 有权
公开(公告)号：US08785981B1
公开(公告)日：2014-07-22
申请号：US14022469
申请日：2013-09-10
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Paul Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/745 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/78696
摘要： A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.

98. 发明授权

US08778768B1 Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain 有权
公开(公告)号：US08778768B1
公开(公告)日：2014-07-15
申请号：US13796418
申请日：2013-03-12
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Paul Chang , Issac Lauer , Jeffrey W. Sleight
IPC分类号： H01L21/336 , H01L29/745
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y40/00 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.

99. 发明申请

US20140183668A1 NANOPORE SENSOR DEVICE 有权
公开(公告)号：US20140183668A1
公开(公告)日：2014-07-03
申请号：US14013598
申请日：2013-08-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Josephine B. Chang , Michael A. Guillorn , Eric A. Joseph , Satyavolu S. Papa Rao
IPC分类号： H01L29/66 , G01N33/543
CPC分类号： H01L29/66007 , B01L3/502707 , G01N33/48721 , G01N33/54373 , H01L29/66
摘要： A pair of electrode plates can be provided by directional deposition and patterning of a conductive material on sidewalls of a template structure on a first dielectric layer. An electrode line straddling the center portion is formed. A dielectric spacer and a conformal conductive layer are subsequently formed. Peripheral electrodes laterally spaced from the electrode line are formed by pattering the conformal conductive layer. After deposition of a second dielectric material layer that encapsulates the template structure, the template structure is removed to provide a cavity that passes through the pair of electrode plates, the electrode line, and the peripheral electrodes. A nanoscale sensor thus formed can electrically characterize a nanoscale string by passing the nanoscale string through the cavity while electrical measurements are performed employing the various electrodes.

100. 发明授权

US08742511B2 Double gate planar field effect transistors 有权
标题翻译：双栅平面场效应晶体管
公开(公告)号：US08742511B2
公开(公告)日：2014-06-03
申请号：US13944480
申请日：2013-07-17
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/78696
摘要： A transistor device includes multiple planar layers of channel material connecting a source region and a drain region, where the planar layers are formed in a stack of layers of a channel material; and a gate conductor formed around and between the planar layers of channel material.
摘要翻译：晶体管器件包括连接源极区和漏极区的沟道材料的多个平面层，其中平面层以通道材料层的叠层形成; 以及形成在沟道材料的平面层之间和之间的栅极导体。

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