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91. 发明申请

WO2018004667A1 TWO TRANSISTOR MEMORY CELL USING HIGH MOBILITY METAL OXIDE SEMICONDUCTORS 审中-公开
标题翻译：两个晶体管存储器使用高迁移率金属氧化物半导体
公开(公告)号：WO2018004667A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040764
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： LE, Van H. , DEWEY, Gilbert William , RADOSAVLJEVIC, Marko , RIOS, Rafael , KAVALIEROS, Jack T. , SHIVARAMAN, Shriram , METERELLIYOZ, Mesut
IPC分类号： H01L27/11 , H01L27/115 , H01L27/108
CPC分类号： H01L27/108 , G11C11/403 , G11C11/405 , H01L27/1225 , H01L29/7869
摘要： A two transistor memory cell is described that uses high mobility amorphous oxide semiconductors. In one example, a sensing transistor has a source and a drain in a first metal layer and a gate between the source and the drain. The gate has a channel formed of a metal oxide semiconductor. A charging transistor has a source and a drain in a second metal layer and a gate channel also formed of metal oxide semiconductor, wherein the source of the charging transistor is coupled to the gate of the sensing transistor, and a gate electrode in a third metal layer is coupled to the gate of the charging transistor.
摘要翻译：描述了使用高迁移率无定形氧化物半导体的双晶体管存储器单元。在一个示例中，感测晶体管具有第一金属层中的源极和漏极以及源极和漏极之间的栅极。该栅极具有由金属氧化物半导体形成的沟道。充电晶体管具有在第二金属层中的源极和漏极以及也由金属氧化物半导体形成的栅极沟道，其中充电晶体管的源极耦合到感测晶体管的栅极，并且栅极电极位于第三金属层耦合到充电晶体管的栅极。

92. 发明申请

WO2018004571A1 WIDE BANDGAP GROUP IV SUBFIN TO REDUCE LEAKAGE 审中-公开
标题翻译：广泛的BANDGAP第四组SUBFIN以减少泄漏
公开(公告)号：WO2018004571A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040129
申请日：2016-06-29
申请人： INTEL CORPORATION
发明人： CHU-KUNG, Benjamin , LE, Van H. , RACHMADY, Willy , METZ, Matthew, V. , KAVALIEROS, Jack, T. , AGRAWAL, Ashish , SUNG, Seung Hoon
IPC分类号： H01L29/78 , H01L29/66 , H01L21/8234 , H01L29/40
CPC分类号： H01L23/49816 , H01L29/1054 , H01L29/66795 , H01L29/785
摘要： A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer.
摘要翻译：将亚鳍层沉积在基板上。鳍层沉积在亚鳍层上。亚鳍层相对于鳍状层具有导带能量偏移以防止亚鳍层中的泄漏。在一个实施例中，亚鳍层包括具有大于鳍状层的带隙的带隙的IV族半导体材料层。

93. 发明申请

WO2018004554A1 QUANTUM DOT DEVICES WITH MODULATION DOPED STACKS 审中-公开
标题翻译：具有调制掺杂堆叠的量子点器件
公开(公告)号：WO2018004554A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/039953
申请日：2016-06-29
申请人： INTEL CORPORATION
发明人： MICHALAK, David J. , PILLARISETTY, Ravi , LE, Van H. , ROBERTS, Jeanette M. , CLARKE, James S. , YOSCOVITS, Zachary R.
IPC分类号： H01L29/778 , H01L29/66 , H01L29/12
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. The doped layer may include a first material and a dopant, the first material may have a first diffusivity of the dopant, the barrier layer may include a second material having a second diffusivity of the dopant, and the second diffusivity may be less than the first diffusivity.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：量子阱堆叠，其包括量子阱层，掺杂层以及设置在掺杂层和量子阱层之间的阻挡层; 以及设置在量子阱堆叠之上的栅极。掺杂层可以包括第一材料和掺杂剂，第一材料可以具有掺杂剂的第一扩散率，阻挡层可以包括具有掺杂剂的第二扩散率的第二材料，并且第二扩散率可以小于第一扩散率。

94. 发明申请

WO2018004537A1 INTEGRATION OF SINGLE CRYSTALLINE TRANSISTORS IN BACK END OF LINE (BEOL) 审中-公开
标题翻译：线后端单晶晶体管的集成（BEOL）
公开(公告)号：WO2018004537A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/039814
申请日：2016-06-28
申请人： INTEL CORPORATION
发明人： LE, Van H. , RADOSAVLJEVIC, Marko , CHU-KUNG, Benjamin , RIOS, Rafael , DEWEY, Gilbert
IPC分类号： H01L29/78 , H01L21/768
摘要： A monocrystalline semiconductor layer is formed on a conductive layer on an insulating layer on a substrate. The conductive layer is a part of an interconnect layer. The monocrystalline semiconductor layer extends laterally on the insulating layer. Other embodiments may be described and/or claimed.
摘要翻译：在衬底上的绝缘层上的导电层上形成单晶半导体层。导电层是互连层的一部分。单晶半导体层在绝缘层上横向延伸。其他实施例可以被描述和/或要求保护。

95. 发明申请

WO2017213647A1 QUANTUM DOT DEVICES WITH BACK GATES 审中-公开
标题翻译：量子点设备与后门
公开(公告)号：WO2017213647A1
公开(公告)日：2017-12-14
申请号：PCT/US2016/036568
申请日：2016-06-09
申请人： INTEL CORPORATION
发明人： ROBERTS, Jeanette M. , PILLARISETTY, Ravi , MICHALAK, David J. , YOSCOVITS, Zachary R. , CLARKE, James S. , LE, Van H.
IPC分类号： H01L29/66 , H01L29/778 , H01L29/12
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：衬底和设置在衬底上的量子阱堆叠。量子阱堆可以包括量子阱层和背栅，并且背栅可以设置在量子阱层和衬底之间。

96. 发明申请

WO2017213646A1 QUANTUM DOT DEVICES WITH MODULATION DOPED STACKS 审中-公开
标题翻译：具有调制掺杂堆叠的量子点器件
公开(公告)号：WO2017213646A1
公开(公告)日：2017-12-14
申请号：PCT/US2016/036565
申请日：2016-06-09
申请人： INTEL CORPORATION
发明人： ROBERTS, Jeanette M. , PILLARISETTY, Ravi , MICHALAK, David J. , YOSCOVITS, Zachary R. , CLARKE, James S. , LE, Van H.
IPC分类号： H01L29/778 , H01L29/66 , H01L29/12 , H01L29/80
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. In some embodiments, a quantum dot device may include: a fin extending away from a base and having insulating material disposed on at least two opposing faces of the fin, wherein the fin includes a quantum well stack and the quantum well stack includes a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：量子阱堆叠，其包括量子阱层，掺杂层以及设置在掺杂层和量子阱层之间的阻挡层; 以及设置在量子阱堆叠之上的栅极。在一些实施例中，量子点器件可以包括：远离基底延伸并且具有设置在鳍的至少两个相对面上的绝缘材料的鳍，其中鳍包括量子阱堆，并且量子阱堆包括量子阱层，掺杂层以及设置在掺杂层和量子阱层之间的阻挡层; 和设置在量子阱堆叠之上的栅极。

97. 发明申请

WO2017151148A1 FIELD EFFECT TRANSISTORS WITH A GATED OXIDE SEMICONDUCTOR SOURCE/DRAIN SPACER 审中-公开
标题翻译：场效应晶体管与门控氧化物半导体源/漏间隔
公开(公告)号：WO2017151148A1
公开(公告)日：2017-09-08
申请号：PCT/US2016/021039
申请日：2016-03-04
申请人： INTEL CORPORATION
发明人： DEWEY, Gilbert W. , RIOS, Rafael , LE, Van H. , KAVALIEROS, Jack T.
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/0924 , B82Y10/00 , H01L21/823821 , H01L21/823864 , H01L29/0653 , H01L29/0673 , H01L29/1054 , H01L29/66795 , H01L29/775 , H01L29/78 , H01L29/785
摘要： FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.
摘要翻译：包括与沟道半导体接口的栅控氧化物半导体隔离物的FET。晶体管可并入非氧化物沟道半导体以及设置在晶体管栅极电极和源极/漏极半导体或源极/漏极接触金属附近的一个或多个氧化物半导体。在有利的实施例中，氧化物半导体将通过施加到栅极电极的电压（即，栅极电压）来门控，以便在绝缘和半导体状态之间切换氧化物半导体，同时在导通之间选通晶体管的非氧化物沟道半导体和关闭状态。

98. 发明申请

WO2014099017A1 LATTICE MISMATCHED HETERO-EPITAXIAL FILM 审中-公开
公开(公告)号：WO2014099017A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/048115
申请日：2013-06-27
申请人： INTEL CORPORATION
发明人： CHU-KUNG, Benjamin , LE, Van H. , CHAU, Robert S. , DASGUPTA, Sansaptak , DEWEY, Gilbert , GOEL, Niti , KAVALIEROS, Jack T. , METZ, Matthew V. , MUKHERJEE, Niloy , PILLARISETTY, Ravi , RACHMADY, Willy , RADOSAVLJEVIC, Marko , THEN, Han Wui , ZELICK, Nancy M.
IPC分类号： H01L21/20 , H01L29/78 , H01L21/336
CPC分类号： H01L29/7391 , H01L29/0676 , H01L29/66242 , H01L29/6625 , H01L29/66356 , H01L29/66393 , H01L29/732 , H01L29/735 , H01L29/737 , H01L29/7371 , H01L29/7436 , H01L29/785
摘要： An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.
摘要翻译：一个实施方案涉及在衬底上形成EPI膜，其中EPI膜具有与衬底不同的晶格常数。 EPI膜和衬底可以包括不同的材料，以共同形成具有例如Si和/或SiGe衬底和III-V或IV膜的异质外延器件。 EPI膜可以是多个EPI层或膜之一，并且膜可以包括彼此不同的材料并且可以直接彼此接触。此外，在掺杂浓度和/或掺杂极性方面，多个EPI层可以与另一个不同地被掺杂。一个实施例包括产生水平取向的异质外延结构。另一实施例包括垂直取向的异质外延结构。异质外延结构可以包括例如双极结型晶体管，异质结双极晶体管，晶闸管和隧道场效应晶体管等。本文描述了其它实施例。

99. 发明申请

WO2014051773A1 SEMICONDUCTOR DEVICE HAVING GERMANIUM ACTIVE LAYER WITH UNDERLYING PARASITIC LEAKAGE BARRIER LAYER 审中-公开
标题翻译：具有下列PARASITIC LEAKAGE BARRIER层的锗激活层的半导体器件
公开(公告)号：WO2014051773A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/047430
申请日：2013-06-24
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , GOEL, Niti , THEN, Han Wui , LE, Van H. , RACHMADY, Willy , RADOSAVLJEVIC, Marko , DEWEY, Gilbert , CHU-KUNG, Benjamin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/28255 , H01L29/0673 , H01L29/1054 , H01L29/1079 , H01L29/1083 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/785 , H01L29/78696
摘要： Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack.
摘要翻译：描述具有底层寄生泄漏阻挡层的具有锗活性层的半导体器件。例如，半导体器件包括设置在衬底上方的第一缓冲层。寄生泄漏屏障设置在第一缓冲层之上。第二缓冲层设置在寄生泄漏屏障的上方。锗活性层设置在第二缓冲层上方。栅电极堆叠设置在锗活性层上方。源极和漏极区域设置在栅极电极堆叠的任一侧上的寄生泄漏屏障之上。

100. 发明申请

WO2014051769A1 METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING 审中-公开
标题翻译：包含非硅器件工程缺陷的方法
公开(公告)号：WO2014051769A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/047385
申请日：2013-06-24
申请人： INTEL CORPORATION
发明人： GOEL, Niti , PILLARISETTY, Ravi , MUKHERJEE, Niloy , CHAU, Robert S. , RACHMADY, Willy , METZ, Matthew V. , LE, Van H. , KAVALIEROS, Jack T. , RADOSAVLJEVIC, Marko , CHU-KUNG, Benjamin , DEWEY, Gilbert , SUNG, Seung Hoon
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/0245 , H01L21/02538 , H01L21/823807 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/0649 , H01L29/0673 , H01L29/1054 , H01L29/1083 , H01L29/267 , H01L29/42392 , H01L29/66469 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/7849 , H01L29/785 , H01L29/7851 , H01L29/78696
摘要： An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.
摘要翻译：一种装置，包括在具有与第一格子结构不同的第二格子结构的缓冲材料中具有匹配的晶格结构的阱材料的阱上具有第一晶格结构的沟道材料的装置。一种包括在缓冲材料中形成沟槽的方法; 在沟槽中形成n型阱材料，n型阱材料具有与缓冲材料的晶格结构不同的晶格结构; 并形成n型晶体管。一种包括计算机的系统，包括处理器，所述处理器包括互补的金属氧化物半导体电路，所述辅助金属氧化物半导体电路包括包括沟道材料的n型晶体管，所述沟道材料在布置在具有不同于第一晶格结构，n型晶体管耦合到p型晶体管。

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