专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20070124636A1 PHASE SYNCHRONIZATION FOR WIDE AREA INTEGRATED CIRCUITS 有权
标题翻译：宽区域集成电路的相位同步
公开(公告)号：US20070124636A1
公开(公告)日：2007-05-31
申请号：US11620309
申请日：2007-01-05
申请人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
发明人： Huy Nguyen , Benedict Lau , Leung Yu , Jade Kizer
IPC分类号： G01R31/28
CPC分类号： G06F1/10 , G06F1/12 , H03L7/00
摘要： A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.
摘要翻译：用于同步计时器件的电路和方法，例如寄存器。由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

92. 发明申请

US20060238974A1 Method and apparatus for venting a chassis 有权
标题翻译：用于排放底盘的方法和装置
公开(公告)号：US20060238974A1
公开(公告)日：2006-10-26
申请号：US11453181
申请日：2006-06-14
申请人： Kenneth Musgrave , Huy Nguyen
发明人： Kenneth Musgrave , Huy Nguyen
IPC分类号： H05K7/20 , G06F1/20
CPC分类号： G06F1/181 , G06F1/20
摘要： A chassis venting apparatus includes a chassis wall base member comprising a first wall. A chassis vent structure is located on the chassis wall base member. A chassis venting passageway is defined between the chassis vent structure and the first wall of the chassis wall base member. The chassis venting apparatus may be, for example, removeably coupled to a chassis or fabricated as part of the chassis in order to provide obscured venting of the chassis and a handle for lifting the chassis.
摘要翻译：底盘排气装置包括一个包括第一壁的底盘壁基件。底盘排气结构位于底盘壁底座上。底盘排气通道限定在底盘排气结构和底盘壁底座构件的第一壁之间。例如，底盘排气装置可以例如可拆卸地联接到底盘或制造为底盘的一部分，以便提供底盘的模糊排气和用于提升底盘的手柄。

93. 外观设计

USD530324S1 Information handling system 有权
公开(公告)号：USD530324S1
公开(公告)日：2006-10-17
申请号：US29235939
申请日：2005-08-08
申请人： Cecilia H. Sun , Darren Blum , Robert Brunner , Kenneth Musgrave , Huy Nguyen , Symon Whitehorn
设计人： Cecilia H. Sun , Darren Blum , Robert Brunner , Kenneth Musgrave , Huy Nguyen , Symon Whitehorn

94. 外观设计

USD528113S1 Information handling system 有权
公开(公告)号：USD528113S1
公开(公告)日：2006-09-12
申请号：US29235973
申请日：2005-08-08
申请人： Cecilia H. Sun , Darren Blum , Robert Brunner , Kenneth Musgrave , Huy Nguyen , Symon Whitehorn
设计人： Cecilia H. Sun , Darren Blum , Robert Brunner , Kenneth Musgrave , Huy Nguyen , Symon Whitehorn

95. 发明申请

US20060192603A1 Wave shaping output driver to adjust slew rate and/or pre-emphasis of an output signal 有权
公开(公告)号：US20060192603A1
公开(公告)日：2006-08-31
申请号：US11068116
申请日：2005-02-28
申请人： Huy Nguyen
发明人： Huy Nguyen
IPC分类号： H03K3/017
CPC分类号： H04L25/0286 , H03K2005/00286 , H04L25/026 , H04L25/03834
摘要： Integrated circuit, system, method and machine readable media embodiments adjust a slew rate and/or a transmit pre-emphasis of an output signal at selected phases during a bit time. A timing circuit provides a plurality of delayed data signals in response to a clock signal. A plurality of adjustable impedance circuits, including a plurality of select circuits, output a plurality of selected delayed data signals to form the output signal having an adjusted slew rate. Delay elements in the timing circuit are also biased from a current of a lock loop circuit to further adjust slew rate of the output signal. Transmit pre-emphasis of the output signal is adjusted by selecting a polarity of a selected delayed data signal in each of the plurality of adjustable impedance circuits. Each adjustable impedance circuit also includes a predriver and driver for adjusting impedance in response to a signal indicating an impedance value. In an embodiment, an integrated circuit is able to operate in multiple modes of operation depending upon the type of output signal, frequency range of the output signal, physical packaging and/or system configuration.

96. 外观设计

USD522505S1 Information handling system 有权
公开(公告)号：USD522505S1
公开(公告)日：2006-06-06
申请号：US29235940
申请日：2005-08-08
申请人： Cecilia H. Sun , Darren Blum , Robert Brunner , Kenneth Musgrave , Huy Nguyen , Symon Whitehorn
设计人： Cecilia H. Sun , Darren Blum , Robert Brunner , Kenneth Musgrave , Huy Nguyen , Symon Whitehorn

97. 发明申请

US20050154547A1 Signalling accommodation 有权
标题翻译：信号住宿
公开(公告)号：US20050154547A1
公开(公告)日：2005-07-14
申请号：US11064925
申请日：2005-02-24
申请人： Huy Nguyen , Benedict Lau
发明人： Huy Nguyen , Benedict Lau
IPC分类号： G06F1/26 , H03K5/153
CPC分类号： G06F1/26
摘要： A receiving unit may implement voltage compensation using a parameters table, an analog calibration component, and/or a digital calibration component. In certain implementation(s), an integrated circuit may include a voltage driver that modifies a supplied compensated voltage based on a feedback signal. The feedback signal may be produced responsive to a distributed voltage version of the compensated voltage, to a received data signal, and to a comparison involving an expected data value. In other implementation(s), a parameters table may be initialized by storing calibration values in entries in association with respective multiple identifications of multiple external points. In still other implementation(s), a particular calibration value of multiple calibration values may be ascertained, with the particular calibration value associated with a particular external point; the particular calibration value may be activated; and data from the particular external point may be received using the particular calibration value. Other implementations are also described.
摘要翻译：接收单元可以使用参数表，模拟校准组件和/或数字校准组件实现电压补偿。在某些实施方案中，集成电路可以包括基于反馈信号修改所提供的补偿电压的电压驱动器。反馈信号可以响应于补偿电压的分布式电压版本，接收的数据信号以及涉及预期数据值的比较来产生。在其他实现中，可以通过将校准值存储在与多个外部点的相应多个标识相关联的条目中来初始化参数表。在另外的实施方式中，可以确定具有与特定外部点相关联的特定校准值的多个校准值的特定校准值; 可以激活特定的校准值; 并且可以使用特定校准值来接收来自特定外部点的数据。还描述了其他实现。

98. 发明申请

US20050058233A1 System and method for adaptive duty cycle optimization 失效
标题翻译：自适应占空比优化的系统和方法
公开(公告)号：US20050058233A1
公开(公告)日：2005-03-17
申请号：US10661225
申请日：2003-09-12
申请人： Huy Nguyen , Roxanne Vu , Leung Yu , Benedict Lau
发明人： Huy Nguyen , Roxanne Vu , Leung Yu , Benedict Lau
IPC分类号： G11C7/10 , G11C7/22 , H04L7/00
CPC分类号： G11C7/1093 , G11C7/1078 , G11C7/22 , G11C7/222
摘要： A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received. This adaptive system and method calibrates a receiver's duty cycle to optimize the receiver timing margin for different data signal types and different slave devices. In one embodiment, a duty cycle correction circuit matches the receiver clock to a predetermined duty cycle. The receiver clock is then configured to have a duty cycle skewed from the predetermined duty cycle based on the specific data signal received. In a receiver system utilizing a clock tree, individual branches of the clock tree are configured to have respective duty cycles skewed to match the duty cycle of a data signal received from a specific transmitting device.
摘要翻译：一种用于配置接收机的系统和方法，使得接收机时钟的占空比与接收到的数据信号的占空比精确匹配。该自适应系统和方法校准接收机的占空比，以优化不同数据信号类型和不同从设备的接收机定时裕度。在一个实施例中，占空比校正电路将接收器时钟与预定的占空比相匹配。然后，接收机时钟被配置为具有基于接收的特定数据信号从预定占空比偏移的占空比。在利用时钟树的接收机系统中，时钟树的各个分支被配置成使各自的占空比歪斜以匹配从特定发送设备接收的数据信号的占空比。

99. 发明申请

US20050052200A1 CALIBRATION METHODS AND CIRCUITS FOR OPTIMIZED ON-DIE TERMINATION 有权
标题翻译：校准方法和优化电路终端的电路
公开(公告)号：US20050052200A1
公开(公告)日：2005-03-10
申请号：US10657605
申请日：2003-09-08
申请人： Huy Nguyen , Vijay Gadde , Benedict Lau
发明人： Huy Nguyen , Vijay Gadde , Benedict Lau
IPC分类号： H03K19/003 , H04L25/02
CPC分类号： H03K19/0005 , H03K5/24 , H03K19/01 , H03K21/08 , H04L25/0278 , H04L25/0298
摘要： Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.
摘要翻译：描述了用于通过一个或多个信号传输线路互连的驱动器管芯和接收器管芯之间的高速通信的管芯端接（ODT）系统和方法。根据一个实施例的ODT控制系统校准并维持终端电阻和驱动电流以产生最佳输出摆幅电压。用于校准参考电阻的比较电路也用于校准驱动电流。一些实施例中的终端元件被分成两个可调节的电阻部分，它们都被设计成最小化容性负载。一部分被优化以产生相对较高的调节范围，而另一部分被优化用于微调和无故障切换。

100. 发明授权

US06806728B2 Circuit and method for interfacing to a bus channel 有权
标题翻译：连接到总线通道的电路和方法
公开(公告)号：US06806728B2
公开(公告)日：2004-10-19
申请号：US09930694
申请日：2001-08-15
申请人： Huy Nguyen , Roxanne Vu , Benedict Lau
发明人： Huy Nguyen , Roxanne Vu , Benedict Lau
IPC分类号： H03K1716
CPC分类号： G06F13/4086
摘要： A circuit and method for interfacing to a bus via an on-die termination pad are shown. The present invention derives an output low reference voltage from an external terminating voltage and an external reference voltage corresponding to the middle of a logic voltage range. A feedback loop is used to compare a voltage at the pad to the output low reference voltage. An on-die termination current sourced to the pad is adjusted accordingly. This allows the present invention to adapt to a variety of external termination voltages. Further, the output low reference voltage is utilized to generate a reference current sourced to an output amplifier, which causes the output swing of the amplifier to track along with the external terminating voltage and the external reference voltage. In another aspect of the present invention, an alternating pattern of logic high and logic low voltage values is transmitted at the pad and received. The received data pattern is compared to the transmitted data pattern to adjust the on-die termination current and the reference current.
摘要翻译：示出了通过片上终端焊盘与总线接口的电路和方法。本发明从外部终端电压和对应于逻辑电压范围中间的外部基准电压得出输出低参考电压。反馈回路用于将焊盘上的电压与输出低参考电压进行比较。相应地调整源于焊盘的片上端接电流。这允许本发明适应各种外部终端电压。此外，输出低参考电压用于产生源自输出放大器的参考电流，这使得放大器的输出摆幅与外部终端电压和外部参考电压一起跟踪。在本发明的另一方面，逻辑高电平和逻辑低电压值的交替模式在焊盘处被传输并被接收。将接收到的数据模式与发送的数据模式进行比较，以调整片上终端电流和参考电流。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式