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91. 发明申请

US20060024703A1 Library on a slide and the use thereof 审中-公开
标题翻译：图书馆幻灯片及其使用
公开(公告)号：US20060024703A1
公开(公告)日：2006-02-02
申请号：US11142590
申请日：2005-06-01
申请人： Lixin Zhang , Betsy Foxman , Carl Marrs , Janet Gilsdorf , Usha Srinivasan , Debashis Ghosh
发明人： Lixin Zhang , Betsy Foxman , Carl Marrs , Janet Gilsdorf , Usha Srinivasan , Debashis Ghosh
IPC分类号： C12Q1/68 , C12M1/34 , C40B40/08
CPC分类号： C12Q1/6837 , C12Q2565/513 , C12Q2523/301
摘要： The present invention relates to compositions and methods for the detection and characterization of nucleic acid sequences and variations in nucleic acid sequences present in multiple genomes. In particular, the present invention provides microarrays possessing two or more whole genomes and methods of making and using the same to detect the presence or absence of target sequences in the plurality of genomes.
摘要翻译：本发明涉及用于检测和表征核酸序列的组合物和方法以及存在于多个基因组中的核酸序列的变化。特别地，本发明提供了具有两个或更多个全基因组的微阵列及其制备和使用它们以检测多个基因组中靶序列的存在或不存在的方法。

92. 发明申请

US20190099428A1 COMPOSITIONS AND METHODS FOR PROPHYLAXIS AND THERAPY FOR MENIERE'S DISEASE 审中-公开
公开(公告)号：US20190099428A1
公开(公告)日：2019-04-04
申请号：US16206734
申请日：2018-11-30
申请人： Lixin Zhang
发明人： Lixin Zhang
IPC分类号： A61K31/53
CPC分类号： A61K31/53
摘要： Provided are articles of manufacture, compositions and methods for prophylaxis and/or therapy for disorders involving dizziness and/or vertigo. The articles of manufacture and compositions contain lamotrigen and/or bupropion. The compositions include pharmaceutical compositions which are intended to alleviate dizziness and/or vertigo. In certain aspects the disclosure includes articles of manufacture and kits which include printed material which provides an indication that the articles or compositions are intended to be used for prophylaxis and/or therapy of Meniere's Disease or a symptom thereof.

93. 发明申请

US20180064716A1 COMPOSITIONS AND METHODS FOR PROPHYLAXIS AND THERAPY FOR MENIERE'S DISEASE 审中-公开
公开(公告)号：US20180064716A1
公开(公告)日：2018-03-08
申请号：US15808223
申请日：2017-11-09
申请人： Lixin Zhang
发明人： Lixin Zhang
IPC分类号： A61K31/53
CPC分类号： A61K31/53
摘要： Provided are articles of manufacture, compositions and methods for prophylaxis and/or therapy for disorders involving dizziness and/or vertigo. The articles of manufacture and compositions contain lamotrigen and/or bupropion. The compositions include pharmaceutical compositions which are intended to alleviate dizziness and/or vertigo. In certain aspects the disclosure includes articles of manufacture and kits which include printed material which provides an indication that the articles or compositions are intended to be used for prophylaxis and/or therapy of Meniere's Disease or a symptom thereof.

94. 发明授权

US09262140B2 Predication supporting code generation by indicating path associations of symmetrically placed write instructions 有权
标题翻译：通过指示对称放置的写指令的路径关联来支持代码生成的预测
公开(公告)号：US09262140B2
公开(公告)日：2016-02-16
申请号：US12123083
申请日：2008-05-19
申请人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
发明人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4451
摘要： A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.
摘要翻译：用于无序指令处理的预测技术提供了低硬件开销的有效的无序执行。一个特殊的操作代码区分了程序代码的统一区域，其中包含依赖于条件分辨率的预测指令。与特殊操作码相关联的字段或操作数指示操作码后面的指令数，并且还包含每个指令与其对应条件路径的关联的指示。区域中的每个条件寄存器写入对于每个条件路径都有相应的寄存器写入，如果对称性尚未存在，编译器插入附加的寄存器写入，形成一组寄存器写操作。因此，统一的指令流可以使用与相同重名资源相关联的寄存器写入进行解码和分派，并且通过执行由解析条件指定的特定指令来解决条件寄存器写入。

95. 发明授权

US09152569B2 Non-uniform cache architecture (NUCA) 有权
标题翻译：非均匀缓存架构（NUCA）
公开(公告)号：US09152569B2
公开(公告)日：2015-10-06
申请号：US12264682
申请日：2008-11-04
申请人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Xiaoxia Wu , Lixin Zhang
发明人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Xiaoxia Wu , Lixin Zhang
IPC分类号： G06F12/02 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0846 , G06F12/0848 , G06F12/123 , G06F2212/225 , G06F2212/271
摘要： In one embodiment, a cache memory includes a cache array including a plurality of entries for caching cache lines of data, where the plurality of entries are distributed between a first region implemented in a first memory technology and a second region implemented in a second memory technology. The cache memory further includes a cache directory of the contents of the cache array and a cache controller that controls operation of the cache memory.
摘要翻译：在一个实施例中，高速缓存存储器包括高速缓存阵列，其包括用于缓存高速缓存行数据的多个条目，其中多个条目分布在以第一存储器技术实现的第一区域和在第二存储器技术中实现的第二区域之间。高速缓冲存储器还包括高速缓存阵列的内容的高速缓存目录和控制高速缓冲存储器的操作的高速缓存控制器。

96. 发明授权

US08756608B2 Method and system for performance isolation in virtualized environments 有权
标题翻译：虚拟化环境中性能隔离的方法和系统
公开(公告)号：US08756608B2
公开(公告)日：2014-06-17
申请号：US12495842
申请日：2009-07-01
申请人： Elmootazbellah N. Elnozahy , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Elmootazbellah N. Elnozahy , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F9/46 , G06F3/00 , G06F13/00 , G06F12/00 , G06F9/50
CPC分类号： G06F9/50 , G06F9/455 , G06F9/5005 , G06F9/5011 , G06F9/5061 , G06F13/00
摘要： A method, a system, an apparatus, and a computer program product for allocating resources of one or more shared devices to one or more partitions of a virtualization environment within a data processing system. At least one user defined resource assignment is received for one or more devices associated with the data processing system. One or more registers, associated with the one or more partitions are dynamically set to execute the at least one resource assignment, whereby the at least one resource assignment enables a user defined quantitative measure (number and/or percentage) of devices to operate when the one or more transactions are executed via the partition. The system enables the one or more devices to execute one or more transactions at a bandwidth/capacity that is less than or equal to the user defined resource assignment and minimizes performance interference among partitions.
摘要翻译：一种用于将一个或多个共享设备的资源分配给数据处理系统内的虚拟化环境的一个或多个分区的方法，系统，设备和计算机程序产品。为与数据处理系统相关联的一个或多个设备接收至少一个用户定义的资源分配。与所述一个或多个分区相关联的一个或多个寄存器被动态地设置为执行所述至少一个资源分配，由此所述至少一个资源分配使得用户定义的定量测量（数量和/或百分比）能够在设备一个或多个事务通过分区执行。该系统使得一个或多个设备能够以小于或等于用户定义的资源分配的带宽/容量来执行一个或多个事务，并且最小化分区之间的性能干扰。

97. 发明授权

US08543770B2 Assigning memory to on-chip coherence domains 有权
标题翻译：将内存分配给片上相干域
公开(公告)号：US08543770B2
公开(公告)日：2013-09-24
申请号：US12787939
申请日：2010-05-26
申请人： William E. Speight , Lixin Zhang
发明人： William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A mechanism is provided for assigning memory to on-chip cache coherence domains. The mechanism assigns caches within a processing unit to coherence domains. The mechanism then assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller. If a cache line is not found within the coherence domain, the memory controller accesses the memory to retrieve the cache line.
摘要翻译：提供了一种用于将存储器分配给片上高速缓存一致性域的机制。该机制将处理单元内的高速缓存分配给相干域。该机制然后将大块内存分配给一致性域。该机制监视在处理单元内的核心上运行的应用程序，以识别应用程序的需求。然后，该机制可以基于在相干域中运行的应用的需要将存储器块重新分配给高速缓存一致性域。当存储器控制器接收高速缓存未命中时，存储器控制器可以查找映射存储器块到高速缓存一致性域的查找表中的地址。侦听请求被发送到连贯域内的缓存。如果在相干域内的高速缓存中找到高速缓存行，则通过直接或通过存储器控制器的高速缓存行的高速缓存将高速缓存行返回到始发高速缓存。如果在相干域内没有找到高速缓存行，则内存控制器访问内存以检索高速缓存行。

98. 发明申请

US20120311265A1 Read and Write Aware Cache 有权
标题翻译：读写写入缓存
公开(公告)号：US20120311265A1
公开(公告)日：2012-12-06
申请号：US13572916
申请日：2012-08-13
申请人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
发明人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F2212/271 , Y02D10/13
摘要： A mechanism is provided in a cache for providing a read and write aware cache. The mechanism partitions a large cache into a read-often region and a write-often region. The mechanism considers read/write frequency in a non-uniform cache architecture replacement polity. A frequently written cache line is placed in one of the farther banks. A frequently read cache line is place in one of the closer banks. The size ration between read-often and write-often regions may be static or dynamic. The boundary between the read-often region and the write-often region may be distinct or fuzzy.
摘要翻译：在缓存中提供了一种机制，用于提供读写感知高速缓存。该机制将大型缓存分区分为常读区域和经常写区域。该机制将读/写频率视为非均匀缓存架构替代策略。经常写入的高速缓存行放置在更远的存储区之一中。经常读取的高速缓存线位于其中一个较近的银行。常读区域和常写区域之间的大小比例可能是静态或动态的。经常读区域和经常写区域之间的边界可能是不同的或模糊的。

99. 发明申请

US20120265944A1 Assigning Memory to On-Chip Coherence Domains 有权
标题翻译：将内存分配给片上一致性域
公开(公告)号：US20120265944A1
公开(公告)日：2012-10-18
申请号：US13454814
申请日：2012-04-24
申请人： William E. Speight , Lixin Zhang
发明人： William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A mechanism for assigning memory to on-chip cache coherence domains assigns caches within a processing unit to coherence domains. The mechanism assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller.
摘要翻译：将存储器分配给片上高速缓存一致性域的机制将处理单元内的高速缓存分配给相干域。该机制将大块内存分配给一致性域。该机制监视在处理单元内的核心上运行的应用程序，以识别应用程序的需求。然后，该机制可以基于在相干域中运行的应用的需要将存储器块重新分配给高速缓存一致性域。当存储器控制器接收高速缓存未命中时，存储器控制器可以查找映射内存块到高速缓存一致性域的查找表中的地址。侦听请求被发送到连贯域内的缓存。如果在相干域内的高速缓存中找到高速缓存行，则通过直接或通过存储器控制器的高速缓存行的高速缓存将高速缓存行返回到始发高速缓存。

100. 发明授权

US08285973B2 Thread completion rate controlled scheduling 有权
标题翻译：线程完成率控制调度
公开(公告)号：US08285973B2
公开(公告)日：2012-10-09
申请号：US12185206
申请日：2008-08-04
申请人： Wael R. El-essawy , Lixin Zhang
发明人： Wael R. El-essawy , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3891
摘要： A method, processor and processing system provide management of per-thread pipeline resource allocation in a simultaneous multi-threaded (SMT) processor by counting indications of instruction completion for each of the threads. The indication may be the commit phase of the pipeline, which indicates results of the pipeline instruction execution are ready for write-back. The completion counts are used in a relative or absolute form to control the pipeline resource allocation. The decode or fetch rates of instructions for the threads can be controlled from the relative or absolute completion counts, providing control of scheduling instructions among the threads for execution by execution pipeline(s). Alternatively, or in combination, the thread priority registers in any thread priority management scheme can be controlled by comparison and/or scaling of the completion counts.
摘要翻译：一种方法，处理器和处理系统通过计数每个线程的指令完成指示来提供同时多线程（SMT）处理器中每线程流水线资源分配的管理。该指示可以是流水线的提交阶段，其指示流水线指令执行的结果准备好回写。完成计数以相对或绝对形式使用以控制流水线资源分配。可以从相对或绝对完成计数来控制线程的解码或提取速率，从而提供线程之间的调度指令的控制，以便由执行流水线执行。或者或组合地，可以通过比较和/或缩放完成计数来控制任何线程优先级管理方案中的线程优先级寄存器。

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