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91. 发明授权

US08163610B2 Fabrication of finned memory arrays 有权
标题翻译：翅片式存储器阵列的制造
公开(公告)号：US08163610B2
公开(公告)日：2012-04-24
申请号：US13117364
申请日：2011-05-27
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/11521 , H01L29/66818 , H01L29/66825 , H01L29/7851 , H01L29/7854 , H01L29/7881
摘要： Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper surface of the fins. A first dielectric layer is formed overlying the isotropically etched fins. A first conductive layer is formed overlying the first dielectric layer. A second dielectric layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the second dielectric layer.
摘要翻译：提供了方法和装置。对于一个实施例，在基板中形成多个散热片，使得散热片从基板突出。在形成多个翅片之后，翅片被各向同性地蚀刻以减小散热片的宽度并绕散热片的上表面。形成覆盖各向同性蚀刻的散热片的第一电介质层。第一导电层形成在第一介电层上。形成覆盖在第一导电层上的第二电介质层。第二导电层形成在第二介电层上。

92. 发明授权

US08144519B2 Programming a flash memory device 有权
标题翻译：编程闪存设备
公开(公告)号：US08144519B2
公开(公告)日：2012-03-27
申请号：US12973110
申请日：2010-12-20
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/06
CPC分类号： G11C16/3454
摘要： An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the program/verify operation. The second verify read operation uses a verify voltage that is substantially close to the maximum verify voltage used during the program/verify step.
摘要翻译：在每个编程脉冲之后执行初始验证读操作。验证电压从第一个字线的初始验证电压开始，并且每个被验证到最大验证电压的字线增加。然后在程序/验证操作之后执行第二验证读操作。第二次验证读取操作使用基本上接近程序/验证步骤期间使用的最大验证电压的验证电压。

93. 发明授权

US08120954B2 Method, apparatus, and system for erasing memory 有权
标题翻译：擦除存储器的方法，设备和系统
公开(公告)号：US08120954B2
公开(公告)日：2012-02-21
申请号：US12833562
申请日：2010-07-09
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C11/5635 , G11C16/0483 , G11C16/107 , G11C16/3404 , G11C16/3409
摘要： Methods, apparatus, and systems may operate to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. An example of applying such a pre-programming operation involves applying a series of voltage pulses to the plurality of multiple level memory cells, verifying a charge stored in the plurality of multiple level memory cells, and erasing the plurality of multiple level memory cells of the memory block based on a result from verifying the charge stored in the plurality of multiple level memory cells.
摘要翻译：方法，装置和系统可以操作以在存储器件的多个多级存储器单元上执行预编程操作。应用这样的预编程操作的示例包括将一系列电压脉冲施加到多个多级存储器单元，验证存储在多个多级存储器单元中的电荷，以及擦除多个多级存储器单元中的多个多级存储器单元存储块基于验证存储在多个多级存储器单元中的电荷的结果。

94. 发明授权

US07995391B2 Multiple select gates with non-volatile memory cells 有权
标题翻译：具有非易失性存储单元的多个选择门
公开(公告)号：US07995391B2
公开(公告)日：2011-08-09
申请号：US12868245
申请日：2010-08-25
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.
摘要翻译：描述与非易失性存储器单元相关联的多个选择门。各种实施例包括多个选择栅极结构，工艺和操作及其对存储器件，模块和系统的适用性。在一个实施例中描述了存储器阵列。存储器阵列包括多个与多个非易失性存储器单元串联耦合的选择栅极。第一选择栅极包括电连接在一起的控制栅极和浮置栅极，第二选择栅极包括由电介质层电隔离的控制栅极和浮置栅极。

95. 发明授权

US07961517B2 Program and read trim setting 有权
标题翻译：编程和读取修剪设置
公开(公告)号：US07961517B2
公开(公告)日：2011-06-14
申请号：US12547218
申请日：2009-08-25
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/102 , G11C16/26
摘要： A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.
摘要翻译：用于在存储器件中设置修剪参数的方法和装置根据观察或测试的编程速度和可靠性提供分配给存储器件部分的多个修整设置。

96. 发明授权

US07952922B2 Method for programming a non-volatile memory device to reduce floating-gate-to-floating-gate coupling effect 有权
标题翻译：用于编程非易失性存储器件以减少浮栅到浮栅耦合效应的方法
公开(公告)号：US07952922B2
公开(公告)日：2011-05-31
申请号：US11448063
申请日：2006-06-06
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3427
摘要： A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data. The method: programs the lower page of predetermined memory cells with first predetermined data and the upper page with second predetermined data. One of the lower page or the upper page of the predetermined memory cells is reprogrammed with the first or second predetermined data, respectively.
摘要翻译：一种用于编程包括多个存储单元的非易失性存储器阵列的方法。每个单元适用于存储数据的下页和上页。该方法：利用第一预定数据对预定存储单元的下页进行编程，并且利用第二预定数据对上页进行编程。分别使用第一或第二预定数据重新编程预定存储单元的下页或上页中的一个。

97. 发明申请

US20110096597A1 PROGRAMMING A FLASH MEMORY DEVICE 有权
标题翻译：编程闪存存储器件
公开(公告)号：US20110096597A1
公开(公告)日：2011-04-28
申请号：US12973110
申请日：2010-12-20
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/34 , G11C16/04 , G11C16/12
CPC分类号： G11C16/3454
摘要： An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the program/verify operation. The second verify read operation uses a verify voltage that is substantially close to the maximum verify voltage used during the program/verify step.
摘要翻译：在每个编程脉冲之后执行初始验证读操作。验证电压从第一个字线的初始验证电压开始，并且每个被验证到最大验证电压的字线增加。然后在程序/验证操作之后执行第二验证读操作。第二次验证读取操作使用基本上接近程序/验证步骤期间使用的最大验证电压的验证电压。

98. 发明授权

US07864575B2 Non-volatile multilevel memory cell programming 有权
标题翻译：非易失性多层存储器单元编程
公开(公告)号：US07864575B2
公开(公告)日：2011-01-04
申请号：US12571518
申请日：2009-10-01
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/12
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell to a first Vt within a lowermost Vt range. The method includes programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell. The method includes programming the upper page of the first wordline cell such that the first Vt is increased to a second Vt, wherein the second Vt is within a Vt range which is then a lowermost Vt range and is positive.
摘要翻译：本公开的实施例提供用于将非易失性多电平存储器单元的阵列编程为多个阈值电压范围的方法，装置，模块和系统。一种方法包括编程第一字线单元的下页以将第一字线单元的阈值电压（Vt）增加到最低Vt范围内的第一Vt。该方法包括在编程第一字线单元的上部页之前对第二字线单元的下部页进行编程。所述方法包括对所述第一字线单元的上部页进行编程，使得所述第一Vt增加到第二Vt，其中所述第二Vt在Vt范围内，其为最低Vt范围并且为正。

99. 发明申请

US20100320523A1 FINNED MEMORY CELLS 有权
标题翻译：精细记忆细胞
公开(公告)号：US20100320523A1
公开(公告)日：2010-12-23
申请号：US12868389
申请日：2010-08-25
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/11521 , H01L29/66818 , H01L29/66825 , H01L29/7851 , H01L29/7854 , H01L29/7881
摘要： For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching.
摘要翻译：对于一个实施例，存储器阵列具有从基板突出的多个翼片。隧道介电层覆盖在翅片上。多个浮动栅极覆盖在隧道介电层上，并且浮栅与从基板突出的翅片一一对应。隔间电介质层覆盖浮栅。控制栅极层覆盖隔间电介质层。每个翅片包括通过各向同性蚀刻圆化的上表面。

100. 发明授权

US07835194B2 Erase operation in a flash memory device 有权
标题翻译：擦除闪存设备中的操作
公开(公告)号：US07835194B2
公开(公告)日：2010-11-16
申请号：US12613254
申请日：2009-11-05
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/344 , G11C16/3418 , G11C16/3427
摘要： A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verified. Adjacent cells are programmed and verified. The parasitic capacitance between the target cells and the adjacent cells causes the threshold voltage of the target cell to increase to a new threshold voltage with the programming of the adjacent cells. A difference between the new threshold voltage and the first threshold voltage is determined. If the difference is greater than or equal to a predetermined threshold, the target cell is soft programmed until the difference is less than the predetermined threshold.
摘要翻译：擦除非易失性存储器件的方法执行块擦除操作。然后对单元进行软编程和擦除验证，以确定阈值电压是否指示已擦除的单元。将目标单元编程为第一阈值电压并进行验证。相邻的单元格被编程和验证。目标单元和相邻单元之间的寄生电容使得相邻单元的编程使目标单元的阈值电压增加到新的阈值电压。确定新阈值电压和第一阈值电压之间的差。如果差值大于或等于预定阈值，则目标单元被软编程，直到该差小于预定阈值。

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