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91. 发明授权

US08669155B2 Hybrid channel semiconductor device and method for forming the same 有权
标题翻译：混合通道半导体器件及其形成方法
公开(公告)号：US08669155B2
公开(公告)日：2014-03-11
申请号：US13142790
申请日：2011-04-11
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/8258
摘要： A hybrid channel semiconductor device and a method for forming the same are provided. The method includes: providing a first semiconductor layer, the first semiconductor layer including an NMOS area and a PMOS area, a surface of the first semiconductor layer being covered by a second semiconductor layer, wherein electrons have higher mobility than holes in one of the first semiconductor layer and the second semiconductor layer, and holes have higher mobility than electrons in the other; forming a first dummy gate structure, and a first source region and a first drain region on respective sides of the first dummy gate structure on the second semiconductor layer in the NMOS area, forming a second dummy gate structure, and a second source region and a second drain region on respective sides of the second dummy gate structure on the second semiconductor layer in the PMOS area; forming an interlayer dielectric layer on the second semiconductor layer and performing planarization; removing the first dummy gate structure and the second dummy gate structure to form a first opening and a second opening; and forming a first gate structure on the one of the first semiconductor layer and the second semiconductor layer in which electrons have higher mobility in the first opening, and forming a second gate structure on the other semiconductor layer in the second opening. The invention can reduce defects in the channel region.
摘要翻译：提供混合通道半导体器件及其形成方法。该方法包括：提供第一半导体层，第一半导体层包括NMOS区域和PMOS区域，第一半导体层的表面被第二半导体层覆盖，其中电子具有比第一半导体层半导体层和第二半导体层，并且空穴在另一个中具有比电子更高的迁移率; 在所述NMOS区域中的所述第二半导体层上形成第一虚拟栅极结构以及所述第一虚拟栅极结构的相应侧上的第一源极区域和第一漏极区域，形成第二虚拟栅极结构，以及第二源极区域和在PMOS区域中的第二半导体层上的第二伪栅极结构的各个侧面上的第二漏极区域; 在所述第二半导体层上形成层间电介质层并进行平坦化; 去除第一虚拟栅极结构和第二虚拟栅极结构以形成第一开口和第二开口; 以及在所述第一半导体层和所述第二半导体层中的所述第一开口中形成具有较高迁移率的第一栅极结构，以及在所述第二开口中的另一半导体层上形成第二栅极结构。本发明可以减少通道区域的缺陷。

92. 发明授权

US08664091B2 Method for removing metallic nanotube 有权
标题翻译：去除金属纳米管的方法
公开(公告)号：US08664091B2
公开(公告)日：2014-03-04
申请号：US13504043
申请日：2011-11-21
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/479
CPC分类号： B82Y40/00 , B82B3/0076
摘要： A method for removing a metallic nanotube, which is formed on a substrate in a first direction, includes forming a plurality of conductors in a second direction crossing the first direction, electrically contacting the plurality of conductors with metallic nanotube, respectively, forming at least two voltage-applying electrodes on the conductors, each of which electrically contacting at least one of the conductors, and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively. Among the conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube.
摘要翻译：一种在第一方向上形成在基板上的金属纳米管的除去方法包括在与第一方向交叉的第二方向上形成多个导体，分别与多个导体与金属纳米管电接触，形成至少两个导体上的施加电压的电极分别与至少一个导体电接触，并且通过电压施加电极分别向至少一些导体施加电压。在分别施加电压的导体中，每两个相邻的导体之间产生电位差，从而烧毁金属纳米管。

93. 发明授权

US08658485B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08658485B2
公开(公告)日：2014-02-25
申请号：US12937321
申请日：2010-06-28
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/823835 , H01L21/823814 , H01L21/823871 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/6656
摘要： There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation.
摘要翻译：提供了一种半导体器件及其制造方法。根据本发明的制造半导体器件的方法包括：在半导体衬底上形成包括栅极和源极和漏极区域的晶体管结构; 进行第一硅化，以在源区和漏区上形成第一金属硅化物层; 在所述衬底上沉积第一介电层，所述第一介电层的顶部与所述栅极区的顶部齐平; 在与第一电介质层中的源极和漏极区对应的部分处形成接触孔; 并且在所述栅极区和所述接触孔中进行第二硅化以形成第二金属硅化物，其中形成所述第一金属硅化物层以防止在所述第二硅化期间在所述源极和漏极区发生硅化。

94. 发明授权

US08633522B2 Semiconductor structure and method for fabricating the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08633522B2
公开(公告)日：2014-01-21
申请号：US13062733
申请日：2010-09-20
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Huicai Zhong
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Huicai Zhong
IPC分类号： H01L29/78
CPC分类号： H01L29/7834 , H01L21/76224 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： A semiconductor structure and a method for fabricating the same. A semiconductor structure includes a semiconductor substrate; a channel region formed in the semiconductor substrate; a gate including a dielectric layer and a conductive layer and formed above the channel region; source and drain regions formed at opposing sides of the gate; first shallow trench isolations embedded into the semiconductor substrate and having a length direction parallel to the length direction of the gate; and second shallow trench isolations, each of which abuts the outer sidewall of the source or the drain region and abuts the first shallow trench isolations, in which the source and drain regions include first seed crystal layers abutting the second shallow trench isolations, and the top surfaces of the second shallow trench isolations are higher than or as high as the top surfaces of the source and drain regions.
摘要翻译：半导体结构及其制造方法。半导体结构包括半导体衬底; 形成在所述半导体衬底中的沟道区; 包括电介质层和导电层并形成在沟道区上方的栅极; 源极和漏极区域形成在栅极的相对侧; 第一浅沟槽隔离物嵌入半导体衬底并具有平行于栅极长度方向的长度方向; 以及第二浅沟槽隔离件，每个隔离件邻接源极或漏极区域的外侧壁并邻接第一浅沟槽隔离物，其中源极和漏极区域包括邻接第二浅沟槽隔离物的第一晶种层和顶部第二浅沟槽隔离物的表面高于或高于源区和漏区的顶表面。

95. 发明授权

US08575654B2 Method of forming strained semiconductor channel and semiconductor device 有权
标题翻译：形成应变半导体通道和半导体器件的方法
公开(公告)号：US08575654B2
公开(公告)日：2013-11-05
申请号：US13059285
申请日：2010-09-19
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/66651 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L29/1054 , H01L29/517 , H01L29/66545
摘要： A method of forming a strained semiconductor channel, comprising: forming a relaxed SiGe layer on a semiconductor substrate; forming a dielectric layer on the relaxed SiGe layer and forming a sacrificial gate on the dielectric layer, wherein the dielectric layer and the sacrificial gate form a sacrificial gate structure; depositing an interlayer dielectric layer, which is planarized to expose the sacrificial gate; etching to remove the sacrificial gate and the dielectric layer to form an opening; forming a semiconductor epitaxial layer by selective semiconductor epitaxial growth in the opening; depositing a high-K dielectric layer and a metal layer; and removing the high-K dielectric layer and metal layer covering the interlayer dielectric layer by planarizing the deposited metal layer and high-K dielectric layer to form a metal gate. A semiconductor device manufactured by this process is also provided.
摘要翻译：一种形成应变半导体沟道的方法，包括：在半导体衬底上形成弛豫的SiGe层; 在弛豫的SiGe层上形成电介质层，并在电介质层上形成牺牲栅极，其中电介质层和牺牲栅极形成牺牲栅极结构; 沉积层间电介质层，其被平坦化以暴露所述牺牲栅极; 蚀刻去除牺牲栅极和电介质层以形成开口; 通过开口中的选择性半导体外延生长形成半导体外延层; 沉积高K电介质层和金属层; 并且通过平坦化沉积的金属层和高K电介质层来去除覆盖层间电介质层的高K电介质层和金属层，以形成金属栅极。还提供了通过该方法制造的半导体器件。

96. 发明授权

US08552504B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US08552504B2
公开(公告)日：2013-10-08
申请号：US13378253
申请日：2011-03-02
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/70
CPC分类号： H01L29/66636 , H01L29/1083 , H01L29/6656 , H01L29/78
摘要： The present invention provides a semiconductor device, which is formed on a semiconductor substrate, comprising a gate stack, a channel region, and source/drain regions, wherein the gate stack is on the channel region, the channel region is in the semiconductor substrate, the source/drain regions are embedded in the semiconductor substrate, and each of the source/drain regions comprises a sidewall and a bottom, a second semiconductor layer being sandwiched between the channel region and a portion of the sidewall distant from the bottom, a first semiconductor layer being sandwiched between the semiconductor substrate and at least a portion of the bottom distant from the sidewall, and an insulating layer being sandwiched between the semiconductor substrate and the other portions of the bottom and/or the other portions of the sidewall. The present invention also provides a method for forming the semiconductor device. The present invention helps preventing the dopants in the source/drain regions from diffusing into the substrate.
摘要翻译：本发明提供一种半导体器件，其形成在半导体衬底上，包括栅极堆叠，沟道区和源极/漏极区，其中栅极堆叠在沟道区上，沟道区位于半导体衬底中，源极/漏极区域被嵌入在半导体衬底中，并且每个源极/漏极区域包括侧壁和底部，第二半导体层夹在沟道区域和远离底部的侧壁的一部分之间，第一半导体层被夹在半导体衬底和远离侧壁的底部的至少一部分之间，绝缘层夹在半导体衬底和侧壁的底部和/或其它部分的其它部分之间。本发明还提供了一种用于形成半导体器件的方法。本发明有助于防止源/漏区中的掺杂剂扩散到衬底中。

97. 发明授权

US08524565B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US08524565B2
公开(公告)日：2013-09-03
申请号：US13063882
申请日：2011-02-16
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device is provided, wherein a step of forming an S/D region comprises: determining an interface region comprising an active region of a partial width abutting an isolation region, and forming an auxiliary layer covering the interface region; removing a semiconductor substrate of a partial thickness in the active region using the auxiliary layer, a gate stack structure and the isolation region as a mask, so as to form a groove; and growing a semiconductor material in the groove for filling into the groove. A semiconductor device having a material of the semiconductor substrate sandwiched between an S/D region and an isolation region is further provided. The present invention is beneficial to reduce current leakage.
摘要翻译：提供一种形成半导体器件的方法，其中形成S / D区域的步骤包括：确定包括邻近隔离区域的部分宽度的有源区域并形成覆盖该界面区域的辅助层的界面区域; 使用辅助层去除有源区域中的部分厚度的半导体衬底，栅极堆叠结构和隔离区域作为掩模，以形成沟槽; 并且在凹槽中生长半导体材料以填充到凹槽中。还提供了具有夹在S / D区域和隔离区域之间的半导体衬底的材料的半导体器件。本发明有益于减少电流泄漏。

98. 发明授权

US08450813B2 Fin transistor structure and method of fabricating the same 有权
标题翻译：翅片晶体管结构及其制造方法
公开(公告)号：US08450813B2
公开(公告)日：2013-05-28
申请号：US12937493
申请日：2010-06-25
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/02 , H01L29/78 , H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L29/7851 , H01L29/66795
摘要： There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures.
摘要翻译：提供鳍式晶体管结构及其制造方法。翅片晶体管结构包括形成在半导体衬底上的鳍片，其中，在用作晶体管结构的沟道区域的鳍片的一部分和衬底之间形成体半导体材料，并且在其余部分之间形成绝缘材料翅片和底物。因此，可以在保持身体结构的优点的同时减小电流泄漏。

99. 发明授权

US08445973B2 Fin transistor structure and method of fabricating the same 有权
标题翻译：翅片晶体管结构及其制造方法
公开(公告)号：US08445973B2
公开(公告)日：2013-05-21
申请号：US12937486
申请日：2010-06-24
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L27/088 , H01L21/02 , H01L29/78 , H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L29/7851 , H01L29/66795
摘要： There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.
摘要翻译：提供鳍式晶体管结构及其制造方法。翅片晶体管结构包括形成在半导体衬底上的鳍片，其中在用作晶体管结构的沟道区域的鳍片的一部分和衬底之间形成绝缘材料，并且在半导体衬底的剩余部分之间形成体半导体材料翅片和底物。由此，可以在保持低成本，高热传递等优点的同时，减小电流泄漏。

100. 发明申请

US20130115743A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20130115743A1
公开(公告)日：2013-05-09
申请号：US13063882
申请日：2011-02-16
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device is provided, wherein a step of forming an S/D region comprises: determining an interface region comprising an active region of a partial width abutting an isolation region, and forming an auxiliary layer covering the interface region; removing a semiconductor substrate of a partial thickness in the active region using the auxiliary layer, a gate stack structure and the isolation region as a mask, so as to form a groove; and growing a semiconductor material in the groove for filling into the groove. A semiconductor device having a material of the semiconductor substrate sandwiched between an S/D region and an isolation region is further provided. The present invention is beneficial to reduce current leakage.
摘要翻译：提供一种形成半导体器件的方法，其中形成S / D区域的步骤包括：确定包括邻近隔离区域的部分宽度的有源区域并形成覆盖该界面区域的辅助层的界面区域; 使用辅助层去除有源区域中的部分厚度的半导体衬底，栅极堆叠结构和隔离区域作为掩模，以形成沟槽; 并且在凹槽中生长半导体材料以填充到凹槽中。还提供了具有夹在S / D区域和隔离区域之间的半导体衬底的材料的半导体器件。本发明有益于减少电流泄漏。

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