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91. 发明专利

JPH0779149A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0779149A
公开(公告)日：1995-03-20
申请号：JP22086493
申请日：1993-09-06
申请人： HITACHI LTD
发明人： ETO JUN , NAKAGOME YOSHINOBU , AOKI MASAKAZU
IPC分类号： H03K19/0175 , H03K19/003
摘要： PURPOSE:To provide a semiconductor integrated circuit device without deteriorating noise margin and causing malfunction even when the distortion of a waveform of a signal through a signal wire increases in the printed circuit board on which the semiconductor integrated circuit device is mounted. CONSTITUTION:Pins P101, P102, P103, P104, P105 receiving a signal level setting signal to decide a comparison voltage and an output signal level for the discrimination of the input signal level are provided in the semiconductor integrated circuit device C1. Since the comparison voltage used to discriminate an output signal level and an input signal level is adjusted in matching a state of noise when the semiconductor integrated circuit device C1 is mounted on a printed circuit board, the noise margin is not deteriorated and no malfunction takes place.

92. 发明专利

JPH02137189A MEMORY CIRCUIT AND DIGITAL DEVICE 失效
公开(公告)号：JPH02137189A
公开(公告)日：1990-05-25
申请号：JP28884188
申请日：1988-11-17
申请人： HITACHI LTD
发明人： HONMA NORIBUMI , NANBU HIROAKI , IDEI YOJI , YAMAGUCHI KUNIHIKO , ETO JUN
IPC分类号： G11C11/41
摘要： PURPOSE:To attain stable memory operation at a high speed by using master and slave latch circuit for one part of a memory LSI constituting circuit. CONSTITUTION:An address buffer 1 to input the clock of a memory LSI, a decoder driver 3, a sense circuit 7, an output buffer 8, control and data buffers 10-12 and a read / write control circuit 9 are latched as the master and slave circuit. Accordingly in

93. 发明专利

JPH0271491A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0271491A
公开(公告)日：1990-03-12
申请号：JP22231788
申请日：1988-09-07
申请人： HITACHI LTD
发明人： ETO JUN , ITO KIYOO , KAWAJIRI YOSHIKI
IPC分类号： G06F1/32 , G11C11/401 , G11C11/404 , G11C11/407 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To drastically reduce the energy consumption of a memory by operating the memory by means of the voltage of a battery. CONSTITUTION:A memory chip 1 is constructed with a battery B as a power source. For example, a memory cell array and a circumferential circuit are operated by the voltage of 1V obtained by reducing the supply voltage value between 1.5V to 3.3V with the use of a voltage limitter L. Consequently, even when the supply voltage is set at any value between the voltage 1.5V to 3.3V, the memory chip can be operated. That is, the voltage limitter is used, the voltage amplitude of a signal in the chip 1 is reduced, the energy consumption is decreased, the accumulated charge of a memory cell MC is secured by writing from the plate of the memory cell MC, the voltage amplitude of data lines D and the inverse of D having large parastic capacity is reduced, and therefore, the low supply voltage and low energy consumption are attained.

94. 发明专利

JPH023161A MEMORY CIRCUIT 失效
公开(公告)号：JPH023161A
公开(公告)日：1990-01-08
申请号：JP14810488
申请日：1988-06-17
申请人： HITACHI LTD
发明人： ETO JUN , ITO KIYOO , KAWAJIRI YOSHIKI
IPC分类号： G11C11/409 , G11C11/21 , G11C11/404 , G11C11/407 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To broadly reduce a data line charging/discharging current and to improve information holding time, an alpha rays resistant sift error property and an S/N by reducing a data line voltage amplitude on memory cell signal amplifying. CONSTITUTION:A memory cell array MA of a memory circuit consists of plural D0, the inverse of D0-Dn and the onverse of Dn, word lines W0-Wn and a memory cell MC. Besides, the plural word lines and the one of data lines are selected with X and Y decoders XD and YD, a signal read out of the memory cell MC is amplified with sense amplifiers SA0-SAn. Besides, while a data line precharging signal the inverse of phiP is 4V at a high electric potential, it becomes 1V at a data line precharging electric potential. Then, sense amplifier driving signals phiSF and the inverse of phiSn become 4V, the sense amplifier becomes an off condition, the inverse of phiP becomes a low electric potential and the word line is selected. Besides, the electric potential difference between the data lines is lowered to a value which is a little larger than the threshold voltage of an MOS-FET constituting the sense amplifier, the electric potential of the inner high electric potential of a memory cell signal is selected and pressure is raised with a terminal to which the MOS-FET for transfer gate is not connected.

95. 发明专利

JPH01264692A SEMICONDUCTOR MEMORY CIRCUIT 失效
公开(公告)号：JPH01264692A
公开(公告)日：1989-10-20
申请号：JP9154188
申请日：1988-04-15
申请人： HITACHI LTD
发明人： ETO JUN , KAWAJIRI YOSHIKI , ITO KIYOO , KAWAHARA TAKAYUKI , WATABE TAKAO
IPC分类号： G11C11/409 , G11C11/34
摘要： PURPOSE:To shorten the access time of a memory without increasing the chip size of the memory by providing a MOS-FET to be controlled by means of the output of a decoder to be made into a transistor (Tr) and a MOS-FET to read and write data on a data line for each data line to a pair of common data line. CONSTITUTION:By an X decoder 2 of a semiconductor memory circuit, one of plural words W0-Wm of an array 1 is selected, and by a Y decoder 3, one of plural data lined D0, the inverse of D0-Dn, the inverse of Dn is selected. The transmission of storage data to plural data lines D3, the inverse of D0-Dn, the inverse of Dn is executed by common data lines I/O and the inverse of I/O, transfer gates T5-T8 controlled by the output signal of the decoder 2 are provided for each pair of data lines D0, the inverse of D0-Dn, the inverse of Dn, the lines I/O and the inverse of I/O are connected to one terminals, and MOS-FET T1 and T2 and MOS-FET T3 and T4 for reading and for writing the signals on the data lines D0, the inverse of D0-Dn, the inverse of Dn are connected to the other terminals.

96. 发明专利

JPH01140495A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH01140495A
公开(公告)日：1989-06-01
申请号：JP29754087
申请日：1987-11-27
申请人： HITACHI LTD
发明人： KIMURA KATSUTAKA , ETO JUN , SHIMOHIGASHI KATSUHIRO
IPC分类号： G11C11/407 , C21C5/40 , G11C11/34 , G11C11/409
摘要： PURPOSE:To prevent the damage of storing information or an erroneous reading and to attain a high speed operation by amplifying a data line and connecting it to input/output line immediately thereafter. CONSTITUTION:A selecting switch SW setting a gate potential at the time of a reading operation below the precharge voltage Vp of data lines D, the inverse of D is discharged to a prescribed potential by the differential amplifying circuit SA of the data lines D, the inverse of D of a low potential side to be conductive thereafter, to read automatically input/output line IO, the inverse of IO signal. Accordingly, as long as the data lines D, the inverse of D are not discharged to the prescribed potential, namely, as long as a fine signal read on the data pair lines D, the inverse of D is not amplified, the selecting switch is not made conductive. The connection of the data lines D, the inverse of D and the input/output line IO, the inverse of IO is not unnecessarily delayed. Thereby, the damage and the erroneous reading of the storing information are prevented to attain the high speed operation.

97. 发明专利

JPH01119985A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH01119985A
公开(公告)日：1989-05-12
申请号：JP27581687
申请日：1987-11-02
申请人： HITACHI LTD
发明人： KIMURA KATSUTAKA , ETO JUN , SHIMOHIGASHI KATSUHIRO
IPC分类号： G11C11/409 , G11C11/34 , G11C11/401 , G11C11/407
摘要： PURPOSE:To prevent erroneous reading by operating a detection amplifying means with the output of a rise detecting circuit of a word line signal or a signal obtained with the delaying of a word line driving signal, whichever is faster, by means of a delay circuit. CONSTITUTION:The driving signal of a sense amplifier SA is not only generated by the output of a rise detecting circuit DCT of word lines W1 and W2 but also outputted by the logical sum between a signal phiXD obtained by delaying, for a constant time, a word line driving signal phiX by means of a delay circuit DLY which is comparatively difficult to generate a directive due to the processing of a disconnection, etc., and a detecting output phia. Further, at the timing of the signal phia or the signal phiXD, whichever is faster, the sense amplifier SA is driven. Consequently, the amplification action of the sense amplifier SA does not start in the middle of the rise of the word lines W1 and W2, the signal of the memory cell MC corresponding to the selected word lines W1 and W2 is sufficiently impressed to respective data lines D1-Dn and the inverse of D1-the inverse of Dn, and then it is amplified. Thus, the erroneous reading is prevented.

98. 发明专利

JPH0198191A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0198191A
公开(公告)日：1989-04-17
申请号：JP25609787
申请日：1987-10-09
申请人： HITACHI LTD
发明人： ETO JUN , KIMURA KATSUTAKA , SHIMOHIGASHI KATSUHIRO
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE:To averaging the lengths of respective signal wirings, to speed up a memory and to stabilize an action by arranging driving signal generation circuits for respective sub arrays in such a way that they are adjacent to a memory array with short wiring paths. CONSTITUTION:A driving signal for a control circuit 15a arranged in a remote place from the driving signal generation circuits for respective sub arrays are supplied by a driving signal generation circuit 17a arranged adjacent to the memory array 12. Thus, the length of a signal wiring L17a can be shortened, and a signal delay by the wiring is reduced. On the other hand, the driving signal for a control circuit 15b arranged near a place from the driving signal generation circuit is supplied by a driving signal generation circuit 17b arranged apart from the memory array 12. Thus, a wiring L17b is prolonged and the signal delay is increased, whereby a difference with a signal delay quantity in the wiring 17a is set small. Consequently, the signal delay in the wirings are set equal and the action of the memory is stabilized.

99. 发明专利

JPS6417294A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS6417294A
公开(公告)日：1989-01-20
申请号：JP17093587
申请日：1987-07-10
申请人： HITACHI LTD
发明人： ETO JUN , KIMURA MASATAKA , SHIMOHIGASHI KATSUHIRO
IPC分类号： G11C11/401 , G11C11/34 , G11C11/409
摘要： PURPOSE:To erase all the contents of a memory at a high speed by providing a data line pre-charge signal control circuit, a sense amplifier driving signal control circuit, and a counter circuit. CONSTITUTION:The titled memory is provided with circuits L2, L3 for holding sense amplifier driving signals phiSA, -phiSA in an active state in order to hold a sense amplifier SA in an operating state, while the contents of a memory MC are erased, a circuit L1 for holding a data pre-charge signal -phiPC in a non-active state, and a circuit AC for generating an address signal Axi in the inside of a chip in order to select and drive successively a word line W, during that time. In this state, the data line pre-charge signal is held in a non-active state, an erasion use data written in the memory cell MC connected to the word line determined in advance is held by the sense amplifier SA by holding the sense amplifier driving signal in an active state, and by operating the address signal generating circuit AC, the word line is activated successively. In such a way, whenever the word line is selected and driven, the contents of plural memory cells connected thereto are erased, and the erasion time can be remarkably shortened.

100. 发明专利

JPS63293793A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS63293793A
公开(公告)日：1988-11-30
申请号：JP12813287
申请日：1987-05-27
申请人： HITACHI LTD
发明人： KUME EIJI , KIMURA KATSUTAKA , ETO JUN , SHIMOHIGASHI KATSUHIRO
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE:To reduce a difference of sense amplifier activating speeds between subblocks and to attain the stable operation of a memory by increasing the driving capacity of a driving circuit having large signal wiring resistance and reducing that of a driving circuit having small signal wiring resistance. CONSTITUTION:When a memory array MA1 having a far distance from a sense amplifier driving circuit is selected, i.e. when the resistance of signal wiring connecting the driving circuit to the subblocks is high, the number of driving transistors (TRs) in the driving circuit is increased and driving capacity is increased, so that the sense amplifier activating speed can be increased. When a memory array MAo having a near distance from sense amplifier driving circuit is selected, i.e., the resistance of signal wiring connecting the driving circuit to the subblocks is low, the number of driving TRs in the driving circuit is reduced and the sense amplifier activating speed is reduced. Consequently the sense amplifier activating speed of the subblock BLK00 can be made equal to that of the BLK10 the sensitivity of the sense amplifiers can be uniformed and the stable operation of the memory can be attained.

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